Recorded Webinar: High Integrity Software Development 08: Automatic Test Vector Generation and Software-In-the-Loop Testing

Complete this request form for immediate access to this webinar and other recorded webinars

Webinar Series (Part 8):

In this webinar we discuss Simulink Design Verifier for automatic test vector generation. This feature of Simulink Design Verifier generates tests to provide model coverage. These tests are then executed against the model and against the generated code compiled locally (Software-In-the-Loop Testing) to ensure that the generated code is functionally equivalent to the model.

Product Focus

Simulink® Design Verifier
DO Qualification Kit

This webinar was recorded on 30 Sep 2009

Contact Information

*Country/Region

Salutation

*First Name

Middle Name

*Last Name

Job Title

Department

Mail Stop

*Company / University

Note: Please enter the official name.

*Street Address 1

Street Address 2

*City

*State

*Zip Code

*Email

*Phone

Extension

Fax

Mobile Phone

Other Information

Are you a MATLAB user?

Yes

Are you a Simulink user?

Yes

Which best describes your application?

Which best describes your industry?

Are you seeking further information on MathWorks products?

Yes

Are you seeking further information on pricing?

Yes

We will not sell or rent your personal contact information. See our privacy policy for details.