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4 Steps To Smarter FPGA Design

Chip design and verification engineers can often write as many as ten lines of test-bench code for every line of RTL code that is implemented in silicon. Despite spending 50% or more of the design cycle on verification tasks, experts estimate that nearly 60% of chips contain functional flaws and require re-spin. Armed with easy to use FPGA design and verification tools, engineers are now deploying FPGAs for accelerated verification as well as for prototyping ASIC and FPGA implementations.

In this scenario, Model-Based Design is helping engineers to efficiently produce FPGA prototypes. Engineers can invest time in algorithm development during the design phase and automate the HDL code-generation process by following a four step approach (Figure 1):

  1. Modeling the DSP algorithm: Using simulation to optimize and test the design
  2. Generating HDL code: Automatically creating HDL code for FPGA prototyping
  3. Verifying HDL code: Reusing the system model as a test-bench to verify the correctness of HDL code
  4. Creating and verifying FPGA prototype: Implementing and verifying the design on FPGAs
Figure 1. Workflow for transforming DSP algorithms into hardware.
Figure 1. Workflow for transforming DSP algorithms into hardware.

Model-Based Design using automatic C and HDL code-generation technologies can speed the development of DSP applications on these newer platforms and can offer support to algorithm designers who are new to HDL and unfamiliar with FPGA design tools.

Automatic HDL code generation is faster than manual hand-coding, allowing engineers to invest some of their time savings to produce higher-quality fixed-point algorithms in the detailed design phase. As a result, engineers can now produce viable FPGA prototypes faster than with traditional, manual workflows.

Automatic HDL Code generation enables engineers to create high-quality FPGA prototypes much faster than would be possible using hand-written HDL code (Figure 2). This is because engineers can invest more time in algorithm development and automatically generate HDL code, which matches the system design specificationIn an attempt to meet aggressive development schedules, engineers may reduce the detailed design phase and begin the hardware development phase sooner. However, this can increase the HDL creation phase as engineers discover that the fixed-point algorithm doesn’t meet system requirements, and have to revisit the detailed-design phase again The resulting time compression can also result in design compromises, such as glue logic or design patches.

Figure 2. Hardware design using Model-Based Design for shorter design cycles, faster prototype development, and rapid design iterations.
Figure 2. Hardware design using Model-Based Design for shorter design cycles, faster prototype development, and rapid design iterations.

Step 1: Modeling the DSP algorithm: Using simulation to optimize and test the design

Using modeling and simulation at the system level, before selecting an architecture, allows engineers to work at a higher level of abstraction. This helps quickly evaluate multiple types of algorithms and architectures for specified design constraints, resulting in better-performing systems.

Step 2: Generate HDL Code – Automatically create HDL code for FPGA prototyping

Most FPGAs are designed using Verilog and VHDL, with handwritten HDL code as the primary source of FPGA design. With a view to select and optimize the best hardware architecture for that DSP implementation, engineers are increasingly looking to automatically generate HDL code from high-level system models. This helps:

  • Quickly prototype the DSP algorithm on FPGAs
  • Iterate on different algorithm design choices faster
  • Reuse algorithmic development work

Automatic HDL code generation can also insert and distribute pipelining stages to help meet speed requirements. Additionally, area-efficient implementations can be generated by using folding techniques (reusing multipliers) without modifying the model.

Step 3: Verify HDL Code – Reuse system model as a test-bench to verify correctness of HDL code

To verify the algorithm implementation in HDL, engineers invest time and effort in manually creating HDL test benches . With HDL cosimulation, engineers can reuse system models to drive stimuli into the HDL simulator and perform system-level analysis of the simulation output interactively. This reduces the time spent on test bench creation, with the added benefit of providing a detailed view of the digital logic and system-level performance.

Step 4: Create and Verify Your FPGA Prototype – Implement and verify your design on FPGAs

FPGA implementation starts once the design has been verified via system-level simulations and HDL cosimulation. Here, engineers gain increased confidence in the success of the algorithm through FPGA-in-the-loop simulation, which is FPGA-based algorithm verification of the algorithm. This helps engineers to run test scenarios faster than using HDL simulation.

The stimulus and analysis parts, the test bench components of the original system model, are used to drive FPGA input stimuli and to analyze the output of the FPGA. As with HDL cosimulation, the results are always available in the system model for analysis. HDL cosimulation offers more visibility into the HDL code, making it ideal for detailed analysis of the problem areas found during FPGA-in-the-loop simulation.


With Model-Based Design, DSP engineers can speed FPGA prototype development and have greater control and confidence in the workflow than in the traditional, manual workflow. The ability to continually refine models and regenerate HDL code automatically enables engineers to do speed the design iteration process. As a result, engineers can create fully tested FPGA and ASIC designs that meet system-level design requirements in a timely manner.

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