FPGA Design, Implementation, and Verification

• Embedded Systems Overview
• Embedded Software Design, Implementation, and Verification
• FPGA Design, Implementation, and Verification
• Embedded Source Code Verification

With MathWorks products you can automatically generate HDL code from your models, speeding up the implementation of your algorithms on FPGAs. You can integrate hand-written HDL code and cosimulate it with your HDL simulator.

Model and Simulate Algorithms for Implementation on FPGAs

Designing algorithms for implementation on FPGAs requires accurate modeling of fixed-point characteristics that affect functional performance. You can create floating-point algorithm specifications in MATLAB and Simulink and then convert them to bit true fixed-point data types up to 128 bits of word length for simulation. Elaborating your design in fixed point at the model level lets you thoroughly explore the fixed-point trade-offs typically associated with an FPGA design.

Generate Synthesizable HDL Code

Automatically generate customizable VHDL and Verilog code from your models that can be synthesized for implementation on an FPGA or ASIC. You can quickly modify the code by updating the model and re-generating the code. The generated code can be passed to downstream third-party tools for synthesis, place and route, and downloading of the final bitstream onto the FPGA.

Automate HDL Verification

Through cosimulation with third-party HDL simulators you can automate the verification of handwritten or automatically generated HDL code – you quickly verify your HDL designs against the original algorithm specification by reusing your models as test benches. This approach eliminates the need to manually transfer test vectors and lets you identify design errors early in the process.