MATLAB Examples

Access FPGA External Memory using MATLAB as AXI Master

This example shows how to use MATLAB as AXI Master to access external DDR memories connected to an FPGA. The example FPGA design instantiates an Altera DDR memory controller for accessing the DDR memories. This memory controller provides a memory-mapped slave interface for read and write operations from the FPGA. The MATLAB as AXI Master feature provides an AXI master IP that allows MATLAB to access any memory-mapped slave IPs in the FPGA. In this example, we demonstrate how to integrate this IP into a Qsys design, and then read and write the DDR memory from MATLAB.



  • Altera® Quartus Prime™ of compatible version
  • Arrow® DECA MAX10 FPGA development kit
  • HDL Verifier™ Support Package for Altera FPGA Boards

Set Up

Step 1: Set up FPGA board Make sure that the DECA board is connected to the host computer via USB JTAG cable.

Step 2: Prepare example in MATLAB

Set up the Altera Quartus Prime tool path. Use your own Altera Quartus Prime installation path when executing the command. For example:

>> hdlsetuptoolpath('ToolName','Altera Quartus II',  'ToolPath','C:\Altera\15.1\quartus\bin64\quartus.exe');

Create a folder outside the scope of your MATLAB installation folder into which you can copy the example files. The folder must be writable. This example assumes that the folder is located at C:\MyTests.

Start MATLAB and set the current directory in MATLAB to the folder you just created. For example:

>> cd C:\MyTests

Copy the example files into current directory by executing this command in MATLAB

>> copyAlteraFPGAExampleFiles('aximaster')

Create a Quartus project for this example. This tcl script would create the Quartus project, and add the design files we created to the project

>> system('quartus_sh -t create_project_deca.tcl')

This command takes a few seconds to finish. When it is done, a Quartus project named "aximaster_deca.qpf" exists in your current directory.

Step 3: Configure Quartus Prime Project To use the MATLAB as AXI Master IP inside Quartus, you can copy the IP to the project directory using the following command:

>>  setupAXIMasterForQuartus('aximaster_deca.qpf')

Next, open the generated Quartus project in GUI mode. You can double-click the project in a file browser, or execute this command in MATLAB:

>> system('quartus aximaster_deca.qpf &')

Step 4: Inspect MATLAB as AXI Master IP in Qsys Design (Optional)

In the Quartus GUI, open the Qsys design file system.qsys and inspect how the MATLAB as AXI Master IP is connected to the DDR controller.

Step 5: Generate FPGA programming file and program FPGA To generate the FPGA programming file , click the "Start Compilation" button in Quartus Prime. It takes about 5 to 10 minutes for Quartus Prime to generate the FPGA Programming file.

After generating the programming file, program the FPGA in MATLAB using the following command:

>> filProgramFPGA('Altera','output_files/aximaster_deca.sof',1)

Read and Write Operations to the FPGA

After programming the FPGA, you can read and write into the AXI slaves connected to the MATLAB as AXI Master IP. In this example, the data will be written to the DDR memory connected to the FPGA, and retrieved back into MATLAB.

First, you need to create the AXI master object in MATLAB

>> h = aximaster('Altera')

Then run these two commands to write a single word (32-bit) of value 100 into DDR memory at address 0 and read it back by using the AXI master object:

>> writememory(h, 0,100)
>> readmemory(h, 0,1)

You can also read and write large vectors of data into DDR memory using a single read/write command in MATLAB. These commands automatically break down the large amount of data into smaller bursts so that they can be transferred via AXI4 protocol. The function uses the largest possible burst size for each burst to maximize the throughput performance. The following commands write 10000 words into DDR memory and read them back. It also checks if the read back data are correct and reports the execution time. It takes about 2 seconds to execute on our computer.

>> tic
>> address = 0;
>> data = 1:100000;
>> writememory(h, address, data);
>> r = readmemory(h, address, 100000);
>> assert(all(r==data));
>> toc