Partly Serial Systolic FIR Filter Implementation
Implement a 32-tap lowpass FIR filter by using the docid:dsp_ref.bvi0_ng-1 block.
The model uses DSP resource sharing of factor 8. Therefore, the model accepts new input samples at least 8 cycles apart.
Open the Model
Open the model. Inspect the block parameters. DSP resource sharing is selected, and all optional ports are enabled. The sharing factor is defined using InitFcn callback function.
Run the Model and Inspect Results
Run the model. Observe the input and output signals in the generated plots.
From the model toolbar, open the Logic Analyzer.
Inspect the rising edges of ready, validIn, and validOut.
Generate HDL Code
To generate HDL code from the Discrete FIR Filter HDL Optimized block, right-click the block and select Create Subsystem from Selection. Then right-click the subsystem and select HDL Code > Generate HDL Code for Subsystem.