MATLAB Examples

IP Core Generation Workflow without an Embedded ARM Processor: Arrow DECA MAX 10 FPGA Evaluation Kit

This example shows how to use the HDL Coder™ IP Core Generation Workflow to develop reference designs for Intel® parts without an embedded ARM® processor present, but which still utilize the HDL Coder™ generated AXI interface to control the DUT. This example uses MATLAB as AXI Master IP from HDL Verifier™ or Intel Qsys™ JTAG to Avalon Master Bridge IP to access the HDL Coder™ generated registers. MATLAB as AXI Master provides access to FPGA registers from MATLAB directly. When you use Intel Qsys™ JTAG to Avalon Master Bridge IP, you can access the FPGA registers using Tcl commands in the Qsys System Console. The FPGA design is implemented on the Arrow DECA MAX 10 FPGA evaluation kit.

Contents

Requirements

  • Intel Quartus™ Prime 16.1
  • Arrow DECA MAX 10 FPGA evaluation kit
  • HDL Coder™ support package for Intel FPGA Boards
  • (Optional) HDL Verifier™ support package for Intel FPGA Boards

Arrow DECA MAX 10 FPGA evaluation kit

Example Reference Designs

There are many designs which will benefit from using the HDL Coder™ IP Core Generation Workflow without using either an embedded ARM® processor or an Embedded Coder™ Support Package, but which still leverages the HDL Coder™ generated AXI4 registers. These designs include:

  1. HDL Verifier™ MATLAB as AXI Master + HDL Coder™ IP Core
  2. Nios® II + HDL Coder™ IP Core
  3. PCIe® Endpoint + HDL Coder™ IP Core
  4. JTAG Master + HDL Coder™ IP Core

There are two reference designs included in this example. The first reference design, "Altera JTAG to AXI Master", uses Quartus IP for the JTAG to AXI Master and therefore requires using the Quartus Tcl console to issue reads and writes. The second reference design, "MATLAB as AXI Master", uses MathWorks IP and a MATLAB command line interface for issuing reads and writes. Note that the MathWorks version requires an HDL Verifier license to use.

The two reference designs are nearly identical, except for the JTAG Master IP shown in the block diagram.

The reference design, "Altera JTAG to AXI Master", uses Qsys™ IP for the JTAG to AXI Master and therefore requires using the Altera® System Console to issue reads and writes:

The plugin_rd.m for this reference design is shown below:

function hRD = plugin_rd()
% Reference design definition
%   Copyright 2016 The MathWorks, Inc.
% Construct reference design object
hRD = hdlcoder.ReferenceDesign('SynthesisTool', 'Altera QUARTUS II');
hRD.ReferenceDesignName = 'Altera JTAG to AXI Master';
hRD.BoardName = 'Arrow DECA MAX 10 FPGA evaluation kit';
% Tool information
hRD.SupportedToolVersion = {'15.1'};
%% Add custom design files
% add custom Qsys design
hRD.addCustomQsysDesign('CustomQsysPrjFile', 'system_soc.qsys');
hRD.CustomConstraints = {'system_soc.sdc','system_setup.tcl'};
%% Add interfaces
% add clock interface
hRD.addClockInterface( ...
    'ClockConnection',     'altpll_0.c0', ...
    'ResetConnection',     'clk_0.clk_reset',...
    'DefaultFrequencyMHz', 100);
% add AXI4 slave interfaces
hRD.addAXI4SlaveInterface( ...
    'InterfaceConnection', 'master_0.master', ...
    'BaseAddress',         '0x0000_0000',...
    'InterfaceType',       'AXI4',...                                          % [ 'AXI4-Lite'| 'AXI4' ]
    'InterfaceID',         'JTAG AXI4 Interface');                             % string name in interface table
% Specify Embedded Coder Support Package to use for Software Interface
hRD.EmbeddedCoderSupportPackage = hdlcoder.EmbeddedCoderSupportPackage.None;  % [ None | Zynq | AlteraSoC ]

The corresponding plugin_rd.m file for the MATLAB as AXI master reference design is located at: plugin_rd.m.

Execute the IP Core Workflow

Using the above reference design you will generate an HDL IP Core that blinks LEDs on the DECA board. The following instruction applies to both reference designs. The files used in the following demonstration are located at:

  • matlab/toolbox/hdlcoder/hdlcoderdemos/customboards/DECA

1. Add the JTAG to AXI Master reference design files to the MATLAB path:

>> addpath(fullfile(matlabroot,'toolbox','hdlcoder','hdlcoderdemos','customboards','DECA'));

2. Set up the Intel Quartus™ tool path. Replace the Quartus™ installation path with your local installation

>> hdlsetuptoolpath('ToolName', 'Altera QUARTUS II', 'ToolPath', 'C:\altera\16.0\quartus\bin64\quartus.exe');

3. Open the Simulink model that implements LED blinking:

open_system('hdlcoder_led_blinking')

4. Launch HDL Workflow Advisor from the hdlcoder_led_blinking/led_counter subsystem by right-clicking the led_counter subsystem, and selecting HDL Code > HDL Workflow Advisor.

5. Select a reference design from the drop down in step 1.2

6. Assign register ports to the "JTAG AXI4 Interface". The table displays the hex offset you can use to access the register.

7. Run the remaining steps in the workflow to generate a bitstream and program the target device.

Notice that unlike the Intel SoC-based reference design, there is no 'Generate Software Interface Model' task. In the reference design "plugin_rd.m", you can disable this task using the following command:

% Disable 'Generate Software Interface Model' task
hRD.EmbeddedCoderSupportPackage = hdlcoder.EmbeddedCoderSupportPackage.None;  %None

Determining Addresses from the IP Core Report

The Base Address for an HDL Coder™ IP Core is defined in the reference design plugin_rd.m with the following command:

% add AXI4 slave interfaces
hRD.addAXI4SlaveInterface( ...
    'InterfaceConnection', 'master_0.master', ...
    'BaseAddress',         '0x0000_0000',...
    'InterfaceType',       'AXI4',...
    'InterfaceID',         'JTAG AXI4 Interface');

For this design, the base address is 0x0000_0000. The offsets can be found in the IP Core Report Register Address Mapping table:

Qsys System Console Tcl Commands for AXI Read and Write

Before we open a System Console, lets look at the basic commands to issue reads and writes. There are a number of flavors of Qsys read and write methods, but we will use the following since all HDL Coder™ generated IP Core registers are currently 32-bits:

% master_write_32 <service-path> <start-address> <list-of-32-bit-values>
% master_read_32  <service-path> <start-address> <size-in-multiples-of-32-bits>

For example, assume we would like to write the 32 bit hex value '0x12345678' to the IP Core register defined by offset '0x100' using a previously defined service path stored in the variable $jtag:

% master_write_32 $jtag 0x100 0x12345678

For more information on these commands you can view help at any time via the following Tcl commands:

% help master_write_32
% help master_read_32

or see the Intel documentation ug_system_console.pdf for more details.

Before you can generate reads and writes, you must first launch a System Console and open a connection to the JTAG Master that will issue the register reads and writes. Refer again to the system diagram below:

To open a connection to JTAG Master, first set a variable that stores the service path (in this case, there is only one master):

% set jtag [lindex [get_service_paths master] 0]

Then use the variable to open the JTAG Master in master mode.

% open_service master $jtag

Now launch the Altera® System Console and enter the commands to open the jtag master:

>> system('C:\altera\15.1\quartus\bin64\sopc_builder\bin\system-console&')

When you are done using the JTAG Master, make sure to close the connection using the following Tcl command:

  close_service master $jtag

HDL Verifier Command Line Interface

If HDL Verifier support package for Intel FPGA boards is installed and the reference design "MATLAB as AXI Master" reference design is selected, then a simple MATLAB command line interface can be use to access the IP core generated by HDL Coder.

First, create the AXI master object:

  >> h = aximaster('Altera')

Then you can issue simple read and write commands. For example, to disable the DUT:

  >> h.writememory('4', 0)

To re-enable the DUT, use the following write command:

  >> h.writememory('4', 1)

To read the current counter value:

  >> h.read('108', 1)

Finally, you are done using the JTAG Master. Delete the object to free up the JTAG resource. If the object is not deleted, other JTAG operations such as programming the FPGA will fail.

  >> delete(h)

Summary

Using a JTAG to AXI Master is a simple way to interface with HDL Coder™ IP core registers in systems which do not have an embedded ARM® processor, such as the MAX 10. This can be used as first step to debug stand-alone HDL Coder™ IP cores, used prior to hand-coding software for soft processors, such as Nios® II, or as an easy way to tune parameters on a running system.