Running an audio filter on live audio input using a Zynq board
In this example, we illustrate how to:
- Model an audio system with Low pass, Band pass and High pass filters
- Implement it on a Zynq board using an audio reference design
The objective of this example is to receive audio input through Zedboard's line input, process it on the FPGA and transmit the processed audio to a speaker. The above figure shows the high-level architecture of such a system. It uses an audio codec to interface to the peripherals and to convert analog to digital signals and vice-versa. The Audio Codec IPs are used to configure the audio codec and for transferring audio data between Zynq Soc and audio codec. The Filter IP is used for audio processing. ARM processor is used to control the type of filter to be used i.e. low pass, band pass or high pass.
Before You Begin
To run this example, you must have the following software and hardware installed and set up:
- HDL Coder Support Package for Xilinx Zynq Platform
- Embedded Coder Support Package for Xilinx Zynq Platform
- Xilinx Vivado version 2016.4
To setup the Zedboard, refer to the "Set up Zynq hardware and tools" section in the Getting Started with HW/SW Co-design Workflow for Xilinx Zynq Platform example. Connect an audio input from a mobile or an MP3 player to LINE IN jack and either earphones or speakers to HPH OUT jack on the Zedboard as shown below.
In the following model, an audio file is used as input to the DUT subsystem, Audio_filter. On simulating this model in Simulink, the processed audio effect can be heard through the Audio Device Writer block and Spectrum Analyzer block displays the spectrogram of the filtered audio output.
modelname = 'hdlcoder_audio_filter_biquad'; open_system(modelname);
Model a system with Low pass, Band pass and High pass filters
Filter coefficients may be generated using a matlab function or in Simulink. In this model filterDesigner tool is used to generate the filter coefficients for each type of filter. Then these filter coefficients are exported and stored as a matlab file. These coefficients will be used to design the filters in Simulink. In this model, discrete IIR filter blocks from Simulink are used as Biquad low pass, band pass or high pass filters depending on the corresponding filter coefficients.
The user can test this model by simulating the model in Simulink. The range of frequencies seen on the Spectrum Analyzer and the audio effect heard through the Audio Device Writer block should vary depending on the type of filter selected. Filter Select block is used to select the type of filtering to be done on the audio input.
Customize the model for Zedboard
In order to implement this model on Zedboard, you must first create a reference design in Vivado which receives audio input on Zedboard and transmits the processed audio data out of Zedboard. For details on how to create a reference design which integrates the audio filter model, refer to Authoring a reference design for audio system on a Zynq board example.
In the reference design, left and right channel audio data are combined together to form a single channel. They are concatenated such that lower 24 bits is the left channel and upper 24 bits is the right channel. In the Simulink model shown above, Data_in is split into 2 channels i.e. left and right accordingly. Their magnitude is divided by 2 and the 2 channels are added together to form a single channel. Filtering is done on this channel.
Data_in and Valid_in are the AXI4-Stream signals. To understand how AXI4-stream interface is used, refer to "Model Streaming Algorithm with Simplified Streaming Protocol" section in the Getting Started with AXI4-Stream Interface in Zynq Workflow example. Data_in contains the audio data to be processed and Valid_in acts as the enable signal. Each filter is mapped to an LED on Zedboard to visually indicate whether the filter is on or off.
FilterSelect input is controlled via AXI4 LITE interface.
Generate HDL IP core with AXI4-Stream Interface
Next, you can start the HDL Workflow Advisor and use the Zynq hardware-software co-design workflow to deploy this design on the Zynq hardware. For a more detailed step-by-step guide, you can refer to the Getting Started with HW/SW Co-design Workflow for Xilinx Zynq Platform example.
1. Set up the Xilinx Vivado synthesis tool path using the following command in the MATLAB command window. Use your own Vivado installation path when you run the command.
hdlsetuptoolpath('ToolName', 'Xilinx Vivado', 'ToolPath', 'C:\Xilinx\Vivado\2016.4\bin\vivado.bat');
2. Add both the IP repository folder and the Zedboard registration file to the MATLAB path using following commands:
3. Start the HDL Workflow Advisor from the DUT subsystem, hdlcoder_audio_filter_model/Audio_filter. The target interface settings are already saved in this example model, so the settings in Task 1.1 to 1.3 are automatically loaded. To learn more about saving target interface settings in the model, you can refer to the Save Target Hardware Settings in Model example.
In Task 1.1, IP Core Generation is selected for Target workflow, and ZedBoard is selected for Target platform.
In Task 1.2, Audio System with AXI4 Stream Interface is selected for Reference Design.
The AXI4-Stream interface is used for transferring audio data between the reference design and the filtering algorithm IP. The AXI4-Stream interface contains data (Data) and control signals such as data valid (Valid), back pressure (Ready), and data boundary (TLAST). At least Data and Valid signals are required for AXI4-Stream IP core generation. In Task 1.3, the Target platform interface table is loaded as shown in the following picture. The audio data stream ports, Valid_in, Data_in, Valid_out and Data_out,are mapped to the AXI4-Stream interfaces, Low_pass_LED, Band_pass_LED, High_pass_LED, Pass_through_LED are mapped to the LEDs on Zedboard and the control parameter port Filter_select is mapped to the AXI4-Lite interface.
The AXI4-Stream interface communicates in master/slave mode, where the master device sends data to the slave device. Therefore, if a data port is an input port, assign it to an AXI4-Stream Slave interface, and if a data port is output port, assign it to an AXI4-Stream Master interface.
3. Right-click Task 3.2, Generate RTL Code and IP Core, and select Run to Selected Task to generate the IP core. You can find the register address mapping and other documentation for the IP core in the generated IP Core Report.
Integrate IP Into AXI4-Stream Audio Compatible Reference Design
Next, in the HDL Workflow Advisor, you run the Embedded System Integration tasks to deploy the generated HDL IP core on Zynq hardware.
1. Run Task 4.1, Create Project. This task inserts the generated IP core into the Audio System with AXI4 Stream Interface reference design. As shown in the first diagram, this reference design contains the IPs to handle audio data in and out of Zedboard. The generated project is a complete Zynq design, including the algorithm part (the generated DUT algorithm IP), and the platform part (the reference design). For details on how to create a reference design which integrates the audio filter model, refer to Authoring a reference design for audio system on a Zynq board example.
2. Click the link in the Result pane to open the generated Vivado project. In the Vivado tool, click Open Block Design to view the Zynq design diagram, which includes the generated HDL IP core, other audio processing IPs and the Zynq processor.
3. In the HDL Workflow Advisor, run the rest of the tasks to generate the software interface model, and build and download the FPGA bitstream. Choose Download programming method in the task Program Target Device to download the FPGA bitstream onto the SD card on the ZedBoard, so your design will be automatically reloaded when you power cycle the ZedBoard.
Generate ARM executable to Tune Parameters on the FPGA Fabric
A software interface model is generated in Task 4.2, Generate Software Interface Model.
1. Before you generate code from the software interface model, comment out the audio input source and audio output sink i.e From Multimedia File, Data Type Conversion, Buffer, Audio Device Writer and Spectrum Analyzer Blocks. These blocks do not need to be run on the ARM processor. The Audio_filter IP is running as *Filtering_Algorithm" on FPGA fabric. The ARM processor is using AXI4-Lite interface for selecting the filter type i.e. Biquad Low pass, band pass, High pass or Pass Through.
- In the generated model, open the Configuration Parameters dialog box.
- Select Solver and set "Stop Time" to "inf".
- From the model menu, select Simulation > Mode > External.
- Click the Run button on the model toolstrip. Embedded Coder builds the model, downloads the ARM executable to the ZedBoard hardware, executes it, and connects the model to the executable running on the ZedBoard hardware.
The type of filter to be used can be selected using the drop down options in FilterSelect block
The filtered audio output can be heard by plugging earphones or speakers to HPH OUT jack on the Zedboard. Depending on the filter selected, the corresponding LED on the Zedboard turns on. In this example, LD0 turns on when Low pass filter is selected, LD1 turns on when Band pass filter is selected, LD2 turns on when High pass filter is selected and LD3 turns on when Pass through (No filter used) option is selected.