QPSK Transmitter and Receiver
This model shows the implementation of a QPSK transmitter and receiver. The receiver addresses practical issues in wireless communications, e.g. carrier frequency and phase offset, timing offset and frame synchronization. The receiver demodulates the received symbols and outputs a simple message to the MATLAB® command line.
Contents
- Available Example Implementations
- Overview
- Structure of the Example
- Transmitter
- AWGN Channel with Frequency Offset and Variable Delay
- Receiver
- Raised Cosine Receive Filter
- AGC
- Coarse Frequency Compensation
- Carrier Synchronizer
- Symbol Synchronizer
- Preamble Detector and Frame Synchronizer
- Data Decoding
- Results and Displays
- Exploring the Example
- References
Available Example Implementations
This example includes both MATLAB and Simulink® implementations:
MATLAB script using System objects: commQPSKTransmitterReceiver.m
Simulink model using blocks: commqpsktxrx.slx
Overview
This example model performs all processing at complex baseband to handle a static frequency offset, a time-varying symbol delay, and Gaussian noise. To cope with the above-mentioned impairments, this example provides a reference design of a practical digital receiver, which includes FFT-based coarse frequency compensation, PLL-based fine frequency compensation, PLL-based symbol timing recovery, frame synchronization, and phase ambiguity resolution. The example showcases a few library blocks in Communications System Toolbox™ that implement key algorithms in the receiver processing, such as the Carrier Synchronizer block for fine frequency compensation, the Symbol Synchronizer block for timing recovery and the *Preamble Detector" block for frame header detection.
Structure of the Example
The top-level structure of the model is shown in the following figure, which includes the Transmitter subsystem, the channel subsystem, and the Receiver subsystem.
The detailed structures of the Transmitter subsystem and the Receiver subsystem are illustrated in the following figures.
The components are further described in the following sections.
Transmitter
- Bit Generation - Generates the bits for each frame
- QPSK Modulator - Modulates the bits into QPSK symbols
- Raised Cosine Transmit Filter - Uses a rolloff factor of 0.5, and upsamples the QPSK symbols by four
Channel
- AWGN Channel with Frequency Offset and Variable Time Delay - Applies the frequency offset, a variable delay, and additive white Gaussian noise to the signal
Receiver
- Raised Cosine Receive Filter - Uses a rolloff factor of 0.5, and downsamples the input signal by two
- Coarse Frequency Compensation - Estimates an approximate frequency offset of the received signal and corrects it
- Carrier Synchronizer - Compensates for the residual frequency offset and the phase offset
- Symbol Synchronizer - Resamples the input signal according to a recovered timing strobe so that symbol decisions are made at the optimum sampling instants
- Preamble Detector - Detect location of the frame header
- Frame Synchronizer - Aligns the frame boundaries at the known frame header
- Data Decoding - Resolves the phase ambiguity caused by the Carrier Synchronizer, demodulates the signal, and decodes the text message
Transmitter
The transmitter includes the Bit Generation subsystem, the QPSK Modulator block, and the Raised Cosine Transmit Filter block. The Bit Generation subsystem uses a MATLAB workspace variable as the payload of a frame, as shown in the following figure. Each frame contains 200 bits. The first 26 bits are header bits, a 13-bit Barker code that has been oversampled by two. The Barker code is oversampled by two in order to generate precisely 13 QPSK symbols for later use in the Data Decoding subsystem. The remaining bits are the payload. The first 105 bits of the payload correspond to the ASCII representation of 'Hello world ###', where '###' is a repeating sequence of '000', '002', '003',..., '099'. The remaining payload bits are random bits. The payload is scrambled to guarantee a balanced distribution of zeros and ones for the timing recovery operation. The scrambled bits are modulated by the QPSK Modulator (with Gray mapping). The modulated symbols are upsampled by four by the Raised Cosine Transmit Filter with a rolloff factor 0.5. The output rate of the Raised Cosine Filter is set to 200k samples/second.
AWGN Channel with Frequency Offset and Variable Delay
The AWGN Channel with Frequency Offset and Variable Delay subsystem first applies the frequency offset and a preset phase offset to the transmit signal. Then it adds a variable delay with a choice of the following two types of delay to the signal:
- Ramp delay - This type of delay is initialized at DelayStart samples, and increases linearly at a rate of DelayStep samples in each frame. When the actual delay reaches one frame, the delay buffer obtains saturation, and it maintains a delay of one frame.
- Triangle delay - This type of delay linearly changes back and forth between MinDelay samples and MaxDelay samples at a rate of DelayStep samples in each frame
The use of multiple delay characteristics allows you to investigate their effects on receiver performance, particularly on the Symbol Synchronizer block. The delayed signal is processed through an AWGN Channel. The diagram of the AWGN Channel with Frequency Offset and Variable Delay subsystem is as shown in the following.
Receiver
Raised Cosine Receive Filter
The Raised Cosine Receive Filter downsamples the input signal by a factor of two, with a rolloff factor of 0.5. It provides matched filtering for the transmitted waveform.
AGC
The phase error detector gain of the phase and timing error detectors is proportional to the received signal amplitude and the average symbol energy. To ensure an optimum loop design, the signal amplitude at the inputs of the carrier recovery and timing recovery loops must be stable. The AGC output power is set to 1/sqrt(Upsampling Factor) (0.5) so that the input amplitude of the Coarse Frequency Compensation subsystem is stable and roughly one. This ensures that the equivalent gains of the phase and timing error detectors keep constant over time. The AGC is placed before the Raised Cosine Receive Filter so that the signal amplitude can be measured with an oversampling factor of four, thus improving the accuracy of the estimate. You can refer to Chapter 7.2.2 and Chapter 8.4.1 of [ 1 ] for details on how to design the phase detector gain.
Coarse Frequency Compensation
The Coarse Frequency Compensation subsystem corrects the input signal with a rough estimate of the frequency offset. The following diagram shows the subsystem, in which the frequency offset is estimated by using a MATLAB System block with the comm.PSKCoarseFrequencyEstimator System object. The compensation is performed by the Phase/Frequency Offset library block. There is usually a residual frequency offset even after the coarse frequency compensation, which would cause a slow rotation of the constellation. The Carrier Synchronizer block compensates for this residual frequency.
Carrier Synchronizer
The fine frequency compensation is performed by a Carrier Synchronizer library block, which implements a phase-locked loop (PLL), described in Chapter 7 of [ 1 ], to track the residual frequency offset and the phase offset in the input signal. The PLL uses a Direct Digital Synthesizer (DDS) to generate the compensating phase that offsets the residual frequency and phase offsets. The phase offset estimate from DDS is the integral of the phase error output of a Loop Filter.
The Damping factor and Normalized loop bandwidth parameters of the block are tunable. Their default values are set to 1 (critical damping) and 0.01 respectively, so that the PLL quickly locks to the intended phase while introducing little phase noise.
Symbol Synchronizer
The timing recovery is performed by a Symbol Synchronizer library block, which implements a PLL, described in Chapter 8 of [ 1 ], to correct the timing error in the received signal. The input of the block is oversampled by two. On average, the block generates one output symbol for every two input samples and hence 100 QPSK symbols per output frame. However, when the channel timing error (delay) reaches symbol boundaries, there will be one extra or missing symbol in the output frame. In that case, the block implements bit stuffing/skipping and generates 101 or 99 QPSK symbols per output frame. So the output of this block is a variable-size signal.
The Damping factor, Normalized loop bandwidth, and Detector gain parameters of the block are tunable. Their default values are set to 1 (critical damping), 0.01 and 5.4 respectively, so that the PLL quickly locks to the correct timing while introducing little timing jitter.
Preamble Detector and Frame Synchronizer
The location of known frame header is detected by a Preamble Detector library block and the frame synchronization is performed by a MATLAB System block using FrameSynchronizer' System object. The Preamble Detector block uses the known frame header (QPSK-modulated Barker code) to correlate against the received QPSK symbols in order to find the location of the frame header. The Frame Synchronizer block uses this location information to align the frame boundaries. It also transforms the variable-size output of the *Symbol Synchronizer block into a fixed-size frame of length 100, which is necessary for the downstream processing. The second output of the block is a boolean scalar indicating if the first output is a valid frame with the desired header and if so, enables the Data Decoding subsystem to run.
Data Decoding
The Data Decoding enabled subsystem performs phase ambiguity resolution, demodulation and text message decoding. The Carrier Synchronizer block may lock to the unmodulated carrier with a phase shift of 0, 90, 180, or 270 degrees, which can cause a phase ambiguity. For details of phase ambiguity and its resolution, please refer to Chapter 7.2.2 and 7.7 in [ 1 ]. The Phase Offset Estimator subsystem determines this phase shift. The Phase Ambiguity Correction & Demodulation subsystem rotates the input signal by the estimated phase offset and demodulates the corrected data. The payload bits are descrambled, and the first 105 payload bits are extracted and stored in a workspace variable. All of the stored bits are converted to characters and printed out to either the MATLAB Command Window or the Simulink Diagnostic Viewer at the end of the simulation.
Results and Displays
When you run the simulation, it displays bit error rate and numerous graphical results.
These plots are shown in the following, starting with the power spectrum of the received signal, with its unknown delay, a frequency offset, and AWGN.
In the following are the constellation diagram and the power spectrum of the Raised Cosine Receive Filter output. Note that the frequency range of the power spectrum plot is reduced by a factor of two, due to the downsampling at the Raised Cosine Receive Filter.
In the following are the constellation diagrams at the output of the Carrier Synchronizer and Symbol Synchronizer blocks respectively.
Exploring the Example
The example allows you to experiment with multiple system capabilities to examine their effect on bit error rate performance. For example, you can view the effect of changing the frequency offset, delay type and on the various displays.
You can tune the Frequency resolution for the Coarse Frequency Compensation subsystem to see the effect of the estimation accuracy and the tolerance to a high noise level. The resolution of the estimate is the frequency spacing between two adjacent FFT points. There is a speed versus accuracy tradeoff when choosing the value of Frequency resolution. To get a more accurate frequency estimate usually requires a smaller Frequency resolution. However, a smaller Frequency resolution also incurs a higher computational burden. On the other hand, if the Frequency resolution is large, then the Carrier Synchronizer block must have a wider frequency tracking range.
This model uses a static frequency offset. In practice, the frequency offset might vary over time. This model can still track a time-varying frequency drift by the Coarse Frequency Compensation subsystem. However, the Coarse Frequency Estimator block takes on discrete values, separated by the Frequency resolution. You might observe jumps between frequency estimates. You can also implement the coarse frequency compensation with a filter to get a smoother estimation output.
You can adjust the PLL design parameters such as Normalized loop bandwidth and Damping factor in the Carrier Synchronizer block to see their effect on pull-in range, convergence time and the estimation accuracy. With a large Normalized loop bandwidth and Damping factor, the PLL can acquire over a greater frequency offset range. However a large Normalized loop bandwidth allows more noise, which leads to a large mean squared error in the phase estimation. "Underdamped systems (with Damping Factor less than one) have a fast settling time, but exhibit overshoot and oscillation; overdamped systems (with Damping Factor greater than one) have a slow settling time but no oscillations." [ 1 ]. For more detail on the design of these PLL parameters, you can refer to Appendix C in [ 1 ].
You can also tune the Normalized loop bandwidth and Damping factor parameters of the Symbol Synchronizer block. The Symbol Synchronizer block relies on a stable constellation which does not rotate over time. So this requires an accurate frequency offset compensation. In this model, if the actual frequency offset exceeds the maximum frequency offset that can be tracked by the current coarse frequency compensation subsystem, you can increase its tracking range by increasing the oversampling factor. Another way to adjust the tracking range is to implement a rotationally-invariant timing error detector (e.g., Gardner timing error detector of the Symbol Synchronizer block, described in Chapter 8.4.1 of [ 1 ]) first and correct the rotation afterwards.
References
1. Michael Rice, "Digital Communications - A Discrete-Time Approach", Prentice Hall, April 2008.