Use distributed pipelining to optimize a design for speed in HDL Coder.
Balance delays in specific parts of a design, without balancing delays on the entire design.
How HDL Coder can automatically balance delays within a model. HDL Coder may introduce additional delays in the HDL implementation for a given model. These delays may be introduced by either
Apply clock rate pipelining to optimize slow paths in your design and thereby reduce latency, increase clock frequency and decrease area usage. For more information on how to use clock-rate
How an indiscrete usage of Simulate rates on a multi- rate design can generate an undesirable HDL code, and provides few recommendations for optimal code generation.
Apply multicycle path constraints in your design to meet timing requirements. Using multicycle path constraints can save area and reduce synthesis run times. For more information, see the