Model and Debug Test Point Signals with HDL Coder™
This example shows how you can mark signals as test points in your Simulink™ model and, after HDL code generation, debug the signals at the top level. Test points are signals that you can use to easily debug and observe the simulation results at various points in your Simulink™ model. You can observe signals designated as test points with a Floating Scope block in a model. In Simulink™, you can designate any signal in a model as a test point.
After HDL code generation, you can observe test point signals at the DUT output ports and further debug the generated code in downstream workflows. This capability makes debugging your design easier because the code generator can propagate test point signals deep within your subsystem hierarchy to the DUT output ports.
Modeling with Test Points
Open the hdlcoder_simulink_test_points model. The DUT is an Enabled Subsystem that calculates two coefficients based on inputs from a Selection Logic and a Comparator.
load_system('hdlcoder_test_points') open_system('hdlcoder_test_points/DUT/MaJ Counter')
To debug internal signals in this model, mark them as test points. For example, you can designate the output signal from the Logical acc block that performs the OR operation as a test point.
- To open the Signal Properties dialog box, right-click the signal and select Properties
- In the Logging and accessibility tab, select Test Point.
To specify the signal as test point at the command line:
- Get handles to the ports of the block.
portHandles = get_param('hdlcoder_test_points/DUT/MaJ Counter/Logical acc', 'portHandles');
PortHandles is a structure with each field as a handle to a block port.
- Get the handle to the output port that creates the target signal line.
outportHandle = portHandles.Outport;
- Set the port parameter TestPoint to 'on'.
Similarly, you can mark the signal at the output of the relational operator Relational 0 block as a test point. Simulink™ displays an indicator on each signal for which you enable the Test point setting. This figure shows the test points that you specified in your model.
The model has three additional test points. These test points are inside the Selection Logic subsystem, the Comparator Subsystem, and the Calculate Coefficients Subsystem blocks.
Enable DUT Output Port Generation for Test Points
After generating HDL code, to debug signals that are designated as test points, enable HDL DUT port generation for the signals. When you generate code for the model, HDL Coder™ propagates these signals to the DUT as an additional output port.
To enable DUT output port generation for the hdlcoder_simulink_test_points model in the Configuration Parameters dialog box:
- Right-click the DUT Subsystem and select HDL Code > HDL Coder Properties.
- On the HDL Code Generation > Global Settings > Ports tab, select Enable HDL DUT port generation for test points.
To specify this setting at the command line, use the EnableTestpoints property.
Specify Generation of Resource Utilization Report
Before you generate HDL code, enable generation of the resource utilization report. When generating code, HDL Coder™ adds a code interface report that displays the test point ports with links to the corresponding test point signals in your Simulink™ model.
To enable DUT output port generation for the hdlcoder_simulink_test_points model, in the Configuration Parameters dialog box, on the HDL Code Generation pane, select Generate resource utilization report.
To specify this setting at the command line, use the ResourceReport property.
Generate HDL Code
To generate HDL code, right-click the DUT Subsystem and select HDL Code > Generate HDL for Subsystem.
When generating code, HDL Coder™ opens the Code Generation report. The report displays a Code Interface Report section that contains links to the test point ports in the Output Ports section.
When you click the links in the test point ports, the code generator highlights the corresponding signals that you designated as test points in your Simulink™ model. Therefore, you can use the report to trace back from the test point port in the generated code to the test point signals in your Simulink™ model.
You can also see the Code Interface Report when HDL Coder™ generates the traceability report. To enable generation of this report, in the Configuration Parameters dialog box, on the HDL Code Generation pane, select Generate traceability report. To specify this report generation at the command line, use the Traceability property with hdlset_param or makehdl.
To see the test point ports in the generated HDL code, open the DUT.v file.
You can see the test point ports at the top level module declaration. These ports have the prefix tp_ and a comment to indicate that they correspond to test point ports. If you specify VHDL as the target language, you can see the test point ports in the entity declaration.
Analyze Generated Model
After HDL code generation, to open the generated model at the command line, enter gm_hdlcoder_test_points.
In the generated model, you see the test points at the DUT output ports connected to a TestPointScope block that is commented out. To observe the simulation results for these signals, uncomment the Scope block, and then run the simulation.
If you navigate the generated model, you can see that the code generator creates an output port at the point where you designated the signal as a test point. HDL Coder™ then propagates these ports to the DUT as additional output ports.