Using Simulink and HDL Coder with Mentor Graphics FPGA Design Tools

• FPGA Design Overview
• MathWorks FPGA Design Solutions
• Altera DSP Builder and HDL Coder
• Using Simulink and HDL Coder with Mentor Graphics FPGA Design Tools
• Xilinx System Generator and HDL Coder

Using MathWorks products with products from Mentor Graphics lets you automate functional verification of Simulink designs and use a vendor-independent flow from Simulink models to target-optimized FPGA implementations.

Automate Functional Verification of FPGA Implementations

Simulink and block libraries let you analyze and design DSP systems, and Simulink models can be used as golden reference models for HDL implementation. Cosimulation of Simulink models with HDL designs modeled in Mentor Graphics ModelSim^® enables you to employ a Simulink design as a test bench for verifying HDL implementations. In addition, HDL Coder produces HDL test benches and simulation scripts for verifying automatically generated HDL code in ModelSim.

Generate Target-Optimized FPGA Netlists from Simulink

Synthesize the vendor-independent HDL code generated by HDL Coder to target-optimized FPGA netlists using Precision Synthesis from Mentor Graphics. HDL Coder generates synthesis scripts for Precision Synthesis, which can be used to produce efficient FPGA implementations for more than 20 FPGA device families.