HDL Code Generation and Verification

Accelerate HDL design and verification using HDL Coder and HDL Verifier

With HDL Coder™ and HDL Verifier™, you can automate much of the time-consuming and error-prone work of implementing algorithms on FPGAs or ASICs. You can quickly evaluate alternative architectures, optimize fixed-point settings, generate HDL code, and prototype on an FPGA. Additionally, you can use generated HDL code for your ASIC implementation.

When implementing your MATLAB® or Simulink® algorithm in hardware, you can use HDL Verifier to check that the HDL design matches the algorithm. This approach enables you to reuse the testbench component of your algorithm to verify the hardware implementation.

Using HDL Coder and HDL Verifier, you can:

  • Perform HDL design iterations in minutes rather than weeks
  • Automatically generate HDL code for FPGA programming or ASIC prototyping and design
  • Verify that your HDL design implementation matches the system design specification
  • Program Xilinx® and Altera® FPGAs from MATLAB and Simulink

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Lockheed Martin Space Systems

Lockheed Martin Space Systems

"We had working code in four months, from start to finish, for a system requiring 5 million gates. Without MathWorks products, it would have taken us at least a year."

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