HDL Code Generation

• HDL Code Generation and Verification Overview
• HDL Code Generation
• HDL Functional Verification

Automatic HDL code generation enables you to rapidly iterate your algorithm and make the right design trade-offs to achieve the best implementation that meets your system requirements.

Generate HDL Code from Simulink Models and MATLAB Algorithms

Use Simulink^® to design system models that contain digital, analog, and software elements.  For the digital section, you can model datapath elements including highly optimized filters and finite state machines, and create custom algorithm IP with MATLAB^®.

You can explore design alternatives, elaborate these models into fixed-point representations, and generate readable HDL code that can be synthesized by industry-standard synthesis tools. Integrate your existing HDL IP into the generated code with HDL Verifier™ black-box technology.

Using automatically generated HDL test benches, you can verify the correct functionality of your design using popular EDA simulators such as Mentor Graphics^® ModelSim^®. 

Speed Design Iterations and Implementation

It’s easy to achieve area-speed trade-offs with HDL Coder™. By using pipelining options and architectural choices, you can rapidly converge on the best hardware implementation of your algorithm. For example, you can choose among cascade, serial, and tree implementations. When your design specification changes, you only need to change the Simulink model and quickly generate HDL code.

Optimize hardware performance by selecting the right implementation architecture. This example uses cascade implementation (top) for one adder and tree implementation (bottom) for another.

Easily Test New Ideas and Targets from the Same Model

By modeling your system at a high level of abstraction, you gain the benefits of design reuse, design portability, and target independence. For example, you can maintain a library of Simulink models for your application and quickly generate a variant HDL implementation without editing a single line of Verilog or VHDL code. You can disseminate your design for development by multiple teams. And you can prototype your implementation in an FPGA and then implement a high-volume design in an ASIC.