HDL Functional Verification

• HDL Code Generation and Verification Overview
• HDL Code Generation
• HDL Functional Verification

More than 50% of hardware project time and resources are spent on verification. That’s because requirements are often ambiguous and many errors are found only after subsystems are integrated late in the hardware phase. You can avoid these errors and costly design rework by using your system-level model as a precise specification for validation, and for verification early in the workflow.

Test Algorithm Implementations Without Writing Test Scripts

Reuse your MATLAB code or Simulink model as the test bench to verify your implementation. Your model serves as an executable specification that describes the digital, analog, and software behaviors that comprise the larger system. Algorithms and tests are designed using MATLAB code or Simulink models, which implementation and verification engineers can then reuse as the test bench for HDL simulators to verify the implementation. This approach eliminates the need to manually write HDL test benches, capture test-vector files for stimulus or response, or write comparison scripts.

Quickly Validate Design Choices for Complex Algorithms

Use your models to perform system-level analysis of your HDL implementation on-the-fly, which gives you insight into the behavior of complex algorithms. You can also use an algorithm model to replace a portion of the HDL implementation to explore different options. By integrating your MATLAB code or Simulink models with ModelSim and other HDL simulators, you immediately see the effects of algorithm, architecture, and optimization choices on the design implementation.

Bridge Workflow Gaps to Reduce Errors and Wasteful Tasks in Algorithm Verification

MathWorks products work with existing HDL functional verification tools, so teams can apply them with minimal disruption. This enables a more collaborative workflow between system and hardware engineers. As a result, development teams spend less time resolving the errors of the manual hand-off process and become more efficient at creating IP, optimizing designs, and verifying the implementation results.