This model shows part of the asymmetric digital subscriber line (ADSL) technology for transmitting data and multimedia information over telephone lines. It illustrates a downstream path from the central office to the end user. It incorporates the discrete multitone (DMT) signaling modulation technique.
The DMT modulator and demodulator subsystems in the model have been updated to allow code reuse when generating code. These subsystems now generate only 10 unique reusable functions compared to the 256 chunks of code for each modulator/demodulator block generated earlier. This leads to shorter compile times and smaller executable sizes.
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The model generates random binary data frames, transmits them according to the ADSL specification, simulates a telephone line using an FIR filter of length 101 and the AWGN Channel block, tries to recover the information from the received data, and computes error statistics. The model uses frame-based processing, thereby processing many bits in each time step. The double connector lines between blocks indicate frame-based signals.
The transmitter portion of the model, shaded in blue at the top of the model, contains two parallel paths. One path (the fast buffer) processes the first 776 bits of each 1552-bit data frame, while the other path (the interleaved buffer) processes the last 776 bits of each data frame. Each path appends eight cyclic redundancy check (CRC) bits to its 776-bit frame, scrambles the bits, and encodes them using a shortened Reed-Solomon code. The scrambling and encoding operations interpret the bits as integers between 0 and 127. In the second path but not the first, a Convolutional Interleaver block interleaves the encoded data. This interleaving operation increases the second path's resistance to burst errors but also its latency. Finally, the data from the two routes is concatenated and modulated. Data from the fast buffer is modulated to the low frequency subcarriers, while data from the interleaved buffer is modulated to the high frequency subcarriers, according to the bit allocation vector b. This example assumes that the bit allocation vector is known and uses the vector to calculate the channel. Enter get_param('commadsl', 'preLoadFcn') to see the calculations involved.
The receiver attempts to undo each operation that the transmitter performs. Much of the receiver's design is straightforward; for example, to undo the actions of the Convolutional Interleaver block, use a Convolutional Deinterleaver block with the same mask parameters. The frequency domain equalizer in the DMT Demodulator subsystem mitigates the channel distortion.
Aligning Frames to Account for Delays. One subtle point in the receiver portion is the Integer Delay block that follows the Convolutional Deinterleaver block. This Integer Delay block delays the deinterleaved data by 800 samples. Because the delay between the original and restored sequences is 40 samples (five shift registers times a maximum delay of 2*(5-1) samples among all shift registers), the extra 800-sample delay ensures that bits are properly aligned in the 840-bit frame.
Two display icons show error statistics for comparisons between the transmitted and received data in the two paths (with and without interleaving). Two other display icons show error statistics based on the CRC bits, where any nonzero bit among the eight CRC bits indicates a frame error.
In each of the display icons, the error statistics consist of the bit error rate, the number of bit errors, and the total number of bits processed.
 Bingham, John A.C., ADSL, VDSL, and Multicarrier Modulation, New York, Wiley, 2000.
 ITU-T Recommendation G.992.1 Asymmetric Digital Subscriber Line (ADSL) Transceivers, Geneva, Telecommunication Standardization Sector of International Telecommunication Union, 1999.
 Maxwell, Kim, "Asymmetric Digital Subscriber Line: Interim Technology for the Next Forty Years," IEEE Communications Magazine, October 1996, pp. 100-106.