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This model shows how to simulate a phase-locked fractional-N frequency synthesizer. The model multiplies the frequency **synFr** of a reference signal by a constant **synN+synM**, to produce a synthesized signal of frequency **synFr(synN+synM)**. A feedback loop maintains the frequency of the synthesized signal at this level. In this example, **synN** is an integer and **synM** is a fraction between 0 and 1. This approach has several advantages, since it enables you to approximate the frequency of the synthesized signal with relatively small values for **synN** and **synM**.

Fractional-N PLL synthesizers attain improved frequency resolution at the expense of increased circuit complexity and increased phase noise (timing jitter) over their non-fractional counterparts. It also enables the use of a larger reference frequency. For more information, see Selected Bibliography. This model implements a fractional-N scheme with analog phase error correction in the phase detector portion of the design. This eliminates the sidebands introduced by switching the loop divider between N and N+1.

There is a simpler example available, PLL-Based Frequency Synthesis Example, which produces a synthesized signal of frequency **synFr*synN/synM**, where **synN** and **synM** are integers.

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The model uses these variables in addition to synN and synM:

**synFr**- frequency of the reference signal**synFq**- quiescent frequency in the Continuous-Time VCO block**synSen**- Voltage-Controlled Oscillator input sensitivity

The model initially assigns values to these variables as follows:

**synN = 10****synM = 0.3****synFr = 10**MHz**synFq = 90**MHz**synSen = 10**MHz/V

The frequency of the synthesized signal at the model's steady state is then **103** MHz. After running the simulation with these values, you can later change them by typing new values in the MATLAB® Command Window, if you want to experiment with the model.

**Blocks and Subsystems in the Example**

Many of the blocks in this model function in the same way as they do in the PLL-Based Frequency Synthesis Example. This section discusses the subsystems that are different.

**Accumulator:** The Accumulator subsystem repeatedly adds the constant **synM** to a cumulative sum. While the sum is less than 1, the output labeled **Carry** is 0. At a time step when the sum becomes greater than or equal to 1, the carry output is 1 and the cumulative sum is reset to its fractional part. The fraction of the time when the carry output is 1 is equal to **synM**, while the fraction of the time when it is 0 is equal to **1-synM**. The accumulator controls the switching between **N** and **N+1** with the carry output. The accumulator output (state) is used to drive the phase compensation circuitry.

**Divide Frequency:** Divide by **N** or **N+1** is implemented using a "swallow" counter scheme, as it would likely be done in hardware. The Divide Frequency subsystem divides the frequency of the synthesized signal by **synN** when the output of the Accumulator subsystem is 0, and divides it by **synN+1** when the output is 1. As a result, the average value that the frequency is divided by is

(1-synM)*synN + synM*(synN+1) = synN + synM = 10.3

**Phase Detector:** Phase-frequency detector and error compensator uses a "dual D" flip-flop for phase detection, along with an integrator, Sample and Hold block, and a simple lead/lag loop filter for error compensation.

When you run the simulation the following are the Scopes that are displayed:

**Control Signals** Scope:

The control signal, which the VCO block uses to maintain the frequency of the synthesized signal

The VCO Control signal: This is seen to settle to a stable value with Phase compensation set to 'on' (default)

**Synthesized Signal** Scope:

The square wave generated based on the VCO output

**RF Spectrum Analyzer** Spectrum Scope:

Displays the frequency spurs.

The switch labeled 'Phase Comp Enable' is set to 'on' by default. In this mode timing jitter and sideband frequency spurs are completely eliminated with just a single frequency spur of -80 dB remaining.

Run the simulation with the compensation off: switch in lower position. Now the graphs will show significant phase jitter and sidebands due to the periodic variations of the VCO control voltage.

The Simulink model outputs a very high quality synthesized output. Real world component limitations can now be introduced to study their effects on the system performance.

Egan, William F., "Fractional-N and Relatives", *Frequency Synthesis by Phase Lock*, (2nd ed., pp. 371-390). N.Y., John Wiley & Sons, 2000.

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