This model shows the use of pseudorandom noise (PN) sequences and multi-stage phase quantization in the design of numerically controlled oscillators (NCOs). Fixed-Point Designer™ is needed to run this model.
An NCO is commonly used as a local oscillator source, as part of a digital receiver implementation. The purpose of this example is to illustrate some of the tradeoffs involved in designing and implementing a fixed-point NCO. The example contains three different NCO implementations.
In this example, dither signals are generated using an internal or external PN Sequence Generator. Dither is used to add noise to the index that is applied to the NCO (cosine) lookup table output values. This is done in order to spread the spurious frequencies ("spurs") throughout the available bandwidth. Without this index dithering, the spurs may be large.
We add the dither signal to the accumulator phase values before further quantization of the accumulated (lookup table index) result. When we increase the number of dither bits beyond the optimal value, the noise floor of the NCO output begins to rise. When we decrease the number of dither bits below the optimal value, the appearance of spurs will decrease the spurious-free dynamic range (SFDR) of the NCO system.
The optimal number of dither bits is usually a small value, based on the implementation of the NCO, the output frequencies of interest, and other system requirements.
NCO Library Block
The NCO Library Block implementation is simply the NCO library block from the DSP System Toolbox™. This implementation uses an internal (15-bit) dither generator and one accumulator phase quantization stage.
First Alternative (Subsystem) Implementation
The First Alternative Implementation is similar to the NCO Library Block implementation. However, it is a subsystem-based implementation, using only Simulink library blocks (along with the Communications System Toolbox™ PN Sequence Generator library block as the external Dither Generator (15-bit)). Note the one accumulator phase quantization stage in blue:
Second Alternative (Subsystem) Implementation
The Second Alternative Implementation is also a subsystem-based implementation. However, unlike the First Alternative Implementation, this subsystem uses two Phase Quantization stages instead of only one stage.
In addition, the Dither Generator (2-bit) uses a much smaller word length as compared to the other implementations (15 bits). Hence, this implementation may utilize fewer hardware resources (that is, it may be a more efficient implementation choice):
Use the Time Scope block to view the time-varying outputs for each of the NCO implementation choices. You can see that the NCO outputs (noisy sinusoids) all have the same frequency, phase, and amplitude characteristics. There are only slight differences in their exact sample values at various points due to their implementation differences.
Use the NCO Cosine Spectrum analyzer blocks to observe the effects of tuning NCO operational parameters and changing the characteristics of the PN Sequence Generator. In particular, you can view the peak Magnitude-squared, dB value at the oscillator frequency and the noise floor at the other frequencies in the spectrum. You can also see the SFDR, which is the difference between the peak magnitude and the highest noise floor ("spur") magnitude value.
Note that although the Second Alternative Implementation uses the least amount of hardware resources, it produces the best SFDR of all three implementations.
To see the effects of dither on SFDR in the Spectrum Analyzer displays (for various NCO frequency and phase offset values):
Enable and disable dither via the Add internal dither parameter in the NCO Library Block implementation.
Change the Number of dither bits parameter in the NCO Library Block implementation (when Add internal dither is on).
Enable and disable dither via connecting and disconnecting the PN Sequence Generator block to or from the alternative subsystem-based NCO implementations.
Change Number of packed bits (and/or other parameters) in the external PN Sequence Generator library blocks for the alternative subsystem-based NCO implementations.
Frequency and Phase
To see the effects of different oscillator frequency and phase offset values on SFDR in the Spectrum Analyzer displays:
Change the Normalized Tuning Freq Register Value.
Change the Normalized Phase Offset Register Value.
Note that this example is simulating an abstraction of the NCO portion of the TI GC4016 Quad Digital Down Converter, and the frequency and phase offset values must be entered in a particular format. More information on how to enter these values may be obtained from the DSP System Toolbox GSM Digital Down Converter exampleexample.