This model shows how to simulate a phase-locked loop (PLL) frequency synthesizer. The model multiplies the frequency (synFr) of a reference signal by a constant synN/synM, to produce a synthesized signal whose frequency is synFr*synN/synM. A feedback loop maintains the frequency of the synthesized signal at this level.
The model uses several variables. Besides
synM, there are
synFr - frequency of the reference signal
synFq - quiescent frequency in the Continuous-Time VCO block
synSen - Voltage-Controlled Oscillator input sensitivity
The model initially assigns values to these variables as follows:
synN = 10
synM = 3
synFr = 30 MHz
synFq = 30 MHz
synSen = 40 MHz/V
The frequency of the synthesized signal is then 100 MHz. After running the simulation with these values, you can later change them by entering new values in the MATLAB® Command Window, if you want to experiment with the model.
Blocks in the Model
The following table lists the most important blocks in the model and describes their purpose.
When you run the simulation, scope windows display these signals:
The control signal, which the Continuous-Time VCO block uses to maintain the frequency of the synthesized signal. This signal initially fluctuates for about 10 microseconds, but then stabilizes to a constant value of 7/4. This occurs when the model reaches a steady state, that is, when the frequency of the synthesized signal is close to 100 MHz.
The synthesized signal, which oscillates back and forth before stabilizing to a square pulse of frequency 100 MHz.
The reference signal, which is a square pulse of frequency 30 MHz.
The Display block at the lower right of the model window displays the frequency of the synthesized signal.
The Pulse Generator block generates the reference signal. The block produces a periodic pulse train. The variable synFr, initially set to 30 MHz, denotes the frequency of the pulse train.
The period of the pulse train is 1/*synFr*. If you want to change the value of the period, change the value of the variable synFr so that the new value of synFr is used in all the blocks whose parameters reference the variable synFr.
Divide Frequency by synM. The Divide Frequency by synM subsystem divides the frequency of the reference signal by the variable synM. With the default values of the variables, the output of the block is a pulse train of frequency 10 MHz, called the frequency-divided reference signal.
Notice that there is also a Divide Frequency by synN subsystem, which divides the frequency of the synthesized signal by the variable synN. The output of this subsystem is called the frequency-divided synthesized signal.
You can change the divisor in these subsystems by changing the value of synM or synN.
The Logical Operator block acts as a phase detector. It uses the XOR operation to compare the frequencies of the frequency-divided reference signal and the frequency-divided synthesized signal.
At steady state, the signal is a pulse train with frequency of 20 MHz. The reason for this is that both inputs to the block have a frequency of 10 MHz, but they are out of phase by 1/4 of their period. As a result, the signal after the XOR operation is a periodic pulse train with frequency 20 MHz.
You can compare the two input signals to the Phase Detector with the output signal by double-clicking their corresponding Scope blocks.
Analog Filter Design. The Analog Filter Design block filters high frequencies out of the signal coming from the phase detector. The block uses a lowpass Butterworth filter. You can use a higher order filter or another filter type to improve the stability of the synthesized signal.
In the steady state of the model, the amplitude of the block's output signal is approximately constant, with a value of 0.5. This is the average value of the output from the phase detector.
A Gain block multiplies the output signal from the Analog Filter Design block by a constant to produce the control signal. The Gain parameter for this block is set to (synFr*synN/synM - synFq) * 2 / synSen. This expression ensures that when the model is at steady state, the frequency of the synthesized signal remains at 100 MHz, even if you make changes to the variables synFq and synSen.
For the default values of the variables, the gain is equal to 7/2. Thus, in the steady state of the model, the output of the Gain block is approximately constant, with a value of 7/4.
The Continuous-Time VCO block generates the synthesized signal (along with the Convert to Square Wave subsystem) and adjusts the frequency of the synthesized signal according to the Voltage-Controlled Oscillator input signal.
When the control signal is close to its steady-state value of 7/4, the Continuous-Time VCO block generates a signal whose frequency is close to synFr*synN/synM, which is 100 MHz for the model's default parameters. If the output frequency drops, the control signal rises, boosting the frequency of the output signal. If the output frequency rises, the control signal falls, lowering the output frequency.
The Quiescent frequency parameter is just the oscillation frequency, synFq. The difference between the block's output signal frequency and the quiescent frequency is proportional to the input signal, interpreted as voltage. The quiescent frequency is set to the variable synFq, which is initially assigned a value of 30 MHz. You can change this value in the Quiescent frequency field, or by changing the value of synFq in the base MATLAB workspace.
The Input sensitivity parameter scales the input voltage, and thus controls the shift from the quiescent frequency. The units of the parameter are hertz per volt. The input sensitivity is set to the variable synSen, which is initially assigned a value of 40 MHz/V.
Changing the values of synFq and synSen will not affect the steady-state frequency of the synthesized signal, because the corresponding change to the gain value exactly compensates for the change.
You can control the simulation parameters by selecting Configuration Parameters from the Simulation menu in the model window. The Max step size parameter determines the maximum step size that the Simulink variable-step solver uses to do calculations. This is set to half the period of the synthesized signal. In general, the Max step size should be less than the smallest period of all signals occurring in the model.