This model shows symbol timing adjustments using interpolation and numerically controlled oscillator (NCO) based control as part of clock recovery in a digital modem as described in the papers referenced below.
Receiver sampling is not synchronized to the received data symbols, and hence there is a need for sample time adjustments in the receiver. The techniques illustrated use signal processing to perform the fixed-rate resampling control loop, and are equivalent to conventional phase-locked loop designs.
The transmitter contains a variable-rate symbol generator. The Symbol frequency is set to 1 MHz by default. The Carrier frequency is set to 21.4 MHz by default. You can control the percent error in the symbol frequency and the carrier frequency in the transmitter by changing the Slider Gain blocks in the transmitter subsystem, and you can view the effects of these errors in the scope displays.
The transmitter uses a pseudorandom sequence generator as a data source. This data is modulated through a QPSK modulator and a Raised Root Cosine (RRC) interpolation filter (the interpolation factor D is set to 8 by default). Carrier offset (via Voltage Controlled Oscillators) and analog lowpass filters are used to create a simulated complex baseband continuous-time (analog) transmitted QPSK signal output.
The receiver takes this transmitted complex baseband continuous-time (analog) QPSK signal as its input, and this data is passed through an ADC and downsampled by 2, using an RRC decimation filter. The symbol clock is recovered from the data using timing recovery. The method used is described in the references listed in the bibliography below.
A Farrow filter structure performs variable fractional sample delays (and thus subsequent variable fractional resampling in downstream blocks). This special FIR filter structure permits simple handling of filter coefficients for an efficient polynomial interpolation formula implementation.
The fractionally resampled data output from the Farrow filter is then passed along to a symbol sampler subsystem (with optional carrier recovery) and, in parallel, to subsystems as part of the feedback control loop for timing error detection. This provides the closed-loop control over the fractional delay in the Farrow filter (and re-sampling in the Symbol Sampler).
Another example Asynchronous Timing in a Bit Timing Recovery ModelAsynchronous Timing in a Bit Timing Recovery Model is available in the SimEvents™ product which is based on this model. The SimEvents model illustrates how to model time-varying clock drift between a transmitter and receiver in a communication system while exploiting their asynchronous behavior.
Structure of the Example
Transmitter. The transmitter subsystem simulates complex baseband continuous-time I/Q data with continuously-variable symbol timing and carrier frequency error controls.
Symbol Timing Error. The symbol timing error percentage is adjusted using the Slider Gain provided.
Carrier Frequency Error. The carrier frequency error percentage is adjusted using the Slider Gain provided.
QPSK Transmitter. The QPSK Transmitter provides continuous-time (analog) complex baseband data for transmission.
Receiver. The QPSK Receiver subsystem performs symbol clock timing recovery with a control loop that includes a variable fractional sample delay Farrow filter, Timing Error Detector and Loop Filter, Symbol Sampling with Optional Carrier Recovery, and Timing Control Unit.
Primary Rx Sampler and Rx RRC Filter. These blocks perform the primary discrete-time downsampling and root raised cosine filtering of the received continuous-time complex baseband data.
Farrow Fractional Delay. The digital Farrow Fractional Delay filter provides variable fractional delay for the received data stream prior to downstream symbol sampling.
Symbol Sampling with Optional Carrier Recovery. This subsystem samples the received data symbols, using the recovered symbol clock to determine when this sampling occurs. Carrier recovery is also performed, based on the Enable carrier recovery check box in the Model Parameters.
Timing Error Detector and Loop Filter. This subsystem detects receiver symbol timing errors. Timing errors are smoothed before they are used as an input to the Timing Control Unit. This implementation is described in H. Meyer et al., Digital Communications Receivers, Chapter 5.4, p. 291.
Timing Control Unit (TCU). The TCU uses an NCO (numerically controlled oscillator) to output the Recovered Symbol Clock and the Fractional Delay Control signals used as part of the timing feedback control loop.
Exploring the Example
This subsystem contains some of the scopes used in this model.
Double-click to control the receiver and control loop settings.
MATLAB® Workspace Variables Used in the example
Results and Displays
The example includes four displays. The Timing Signals scope shows the Timing Error signal output of the Timing Error Detector subsystem, as well as the TCU Control input signal and the Fractional Delay Control output signal as part of the NCO-based timing loop control section.
The Carrier Recovery Signals scope shows the Phase Error Estimate, Frequency Error Estimate, and NCO Control signals used in the Decision Aided Carrier Phase Recovery Loop underneath the Symbol Sampler / Carrier Recovery subsystem. Note that if the Enabled carrier recovery check box is not selected in the Model Parameters, then this scope is not updated (because carrier recovery is disabled in the Symbol Sampling with Optional Carrier Recovery subsystem).
The Symbol Clocks and Data scope shows the transmitter and (recovered) receiver symbol clock signals, as well as the received I/Q data.
The Enabled Scatter Plot shows the effects of timing errors in a scatter plot display.
1. Gardner, F., "Interpolation in Digital Modems - Part I: Fundamentals," IEEE Transactions on Communications, Vol. 41, No. 3, March 1993, pp. 501-507.
2. Erup, L., F. Gardner, and R. Harris, "Interpolation in Digital Modems - Part II: Implementation and Performance," IEEE Transactions on Communications, Vol. 41, No. 6, June 1993, pp. 998-1008.
3. H. Meyr et. al., "Digital Communications Receivers", Section 5.4.