# Documentation

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# General CRC Generator

Generate CRC bits according to generator polynomial and append to input data frames

## Library

CRC sublibrary of Error Correction and Detection

## Description

The General CRC Generator block generates cyclic redundancy code (CRC) bits for each input data frame and appends them to the frame. This block accepts a binary column vector input signal.

You specify the generator polynomial for the CRC algorithm using the Generator polynomial parameter. This block is general in the sense that the degree of the polynomial does not need to be a power of two. You represent the polynomial in one of these ways:

• As a polynomial character vector such as `'x^3 + x^2 + 1'`.

• As a binary row vector containing the coefficients in descending order of powers. For example, `[1 1 0 1]` represents the polynomial x3 + x2 + 1.

• As an integer row vector containing the powers of nonzero terms in the polynomial, in descending order. For example, ```[3 2 0]``` represents the polynomial x3 + x2 + 1.

You specify the initial state of the internal shift register by the Initial states parameter. The Initial states parameter is either a scalar or a binary row vector of length equal to the degree of the generator polynomial. A scalar value is expanded to a row vector of length equal to the degree of the generator polynomial. For example, the default initial state of `[0]` is expanded to a row vector of all zeros.

You specify the number of checksums that the block calculates for each input frame by the Checksums per frame parameter. The Checksums per frame value must evenly divide the size of the input frame. If the value of Checksums per frame is k, the block does the following:

1. Divides each input frame into k subframes of equal size

2. Prefixes the Initial states vector to each of the k subframes

3. Applies the CRC algorithm to each augmented subframe

4. Appends the resulting checksums at the end of each subframe

5. Outputs concatenated subframes

If the size of the input frame is m and the degree of the generator polynomial is r, the output frame has size m + k * r.

This block supports `double` and `boolean` data types. The block inherits the output data type from the input signal.

### Example

Suppose the size of the input frame is 10, the degree of the generator polynomial is 3, Initial states is `[0]`, and Checksums per frame is `2`. The block divides each input frame into two subframes of size 5 and appends a checksum of size 3 to each subframe, as shown below. The initial states are not shown in this example, because an initial state of `[0]` does not affect the output of the CRC algorithm. The output frame then has size 5 + 3 + 5 + 3 = 16.

### Example of Cyclic Redundancy Check Encoding

This example clarifies the operation of the General CRC Generator block by comparing the generated CRC bits from the library block with those generated from primitive Simulink® blocks. To open the model, enter `doc_crcgen` at the MATLAB® command line.

For a known input message with a length of 6 bits, the model generates CRC bits for a generator polynomial, $g\left(x\right)={x}^{3}+x+\text{​}1$, and a specific initial state of the register.

You can experiment with different initial states by changing the value of Initial states prior to running the simulation. For all values, the comparison (generated CRC bits from the library block with those generated from primitive Simulink blocks) holds true.

Using the General CRC Generator block allows you to easily specify the generator polynomial (especially for higher order polynomials).

### Signal Attributes

The General CRC Generator block has one input port and one output port. Both ports support binary column vector signals.

## Parameters

Generator polynomial

A polynomial character vector, a binary row vector in descending order of powers, or an integer row vector in descending order of powers.

Initial conditions

Binary scalar or a binary row vector of length equal to the degree of the generator polynomial, specifying the initial state of the internal shift register.

Direct method

When you select this check box, the object uses the direct algorithm for CRC checksum calculations. When you clear this check box, the object uses the non-direct algorithm for CRC checksum calculations.

Reflect input bytes

When you select this check box, the block flips the input data on a bytewise basis prior to entering the data into the shift register. For this application, the input frame length (and any current input frame length for variable-size signals) divided by the value for the Checksums per frame parameter must be a multiple of eight. When you clear this check box, the block does not flip the input data.

Reflect checksums before final XOR

When you select this check box, the block flips the CRC checksums around their centers after the input data are completely through the shift register. When you clear this check box, the block does not flip the CRC checksums.

Final XOR

Specify the value with which the CRC checksum is to be XORed as a binary scalar or vector. The block applies the XOR operation just prior to appending the input data. The vector length is the degree of the generator polynomial that you specify in the Generator polynomial parameter. When you specify the final XOR value as a scalar, the block expands the value to a row vector with a length equal to the degree of the generator polynomial. The default value of this parameter is `0`, which is equivalent to no XOR operation.

Checksums per frame

Specify the number of checksums the block calculates for each input frame. This value must be a positive integer. The input frame length (and any current input frame length for variable-size signals) must be a multiple of this parameter value.

## Algorithm

For a description of the CRC algorithm as implemented by this block, see Cyclic Redundancy Check Codes in Communications System Toolbox™ User's Guide.

## References

[1] Sklar, Bernard, Digital Communications: Fundamentals and Applications. Englewood Cliffs, N.J., Prentice-Hall, 1988.

[2] Wicker, Stephen B., Error Control Systems for Digital Communication and Storage, Upper Saddle River, N.J., Prentice Hall, 1995.

## Pair Block

General CRC Syndrome Detector