General CRC Generator HDL Optimized

Generate CRC code bits and append to input data, optimized for HDL code generation

Library

CRC sublibrary of Error Correction and Detection

Description

This hardware-friendly CRC generator block, like the General CRC Generator block, generates the CRC bits and appends them to the input message bits. The output consists of CRC checksum plus the message. With the General CRC Generator HDL Optimized block, the processing is optimized for HDL code generation. Instead of processing an entire frame at once, the block processes samples of data. Control signals are added at both input and output for easy data synchronization.

Signal Attributes

The General CRC Generator HDL Optimized block has four input ports and four output ports.

PortDirectionDescriptionData Type
dataInInputMessage data. Data can be a column vector of binary values, or a scalar integer representing several bits. That is, vector input [0,0,0,1,0,0,1,1] is equivalent to uint8 input 19. Data width must be less than or equal to the CRC length, and the CRC length must be divisible by the data width. For example, for CRC-CCITT/CRC-16, the valid data widths are 16, 8, 4, 2 and 1.

Vector: double, boolean, or fixdt(0,1,0)

Scalar : unsigned integer (uint8/16/32) or fixdt(0,N,0)

startInInputIndicates the start of a frame of data. Boolean or fixdt(0,1,0)
endInInputIndicates the end of a frame of data. Boolean or fixdt(0,1,0)
validInInputIndicates that input data is valid. Boolean or fixdt(0,1,0)
dataOutOutputMessage data with the checksum appended. The data width and type is the same as the input data port. Same as dataIn
startOutOutputIndicates the start of a frame of data. Boolean or fixdt(0,1,0)
endOutOutputIndicates the end of a frame of data, including checksum. Boolean or fixdt(0,1,0)
validOutOutputIndicates that output data is valid. Boolean or fixdt(0,1,0)

Dialog Box

Polynomial

A double, boolean, or fixdt(0,1) row or column vector specifying the polynomial, in descending order of powers. CRC length is length(polynomial)-1. The default value is [1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1].

Initial state

A double, boolean, or fixdt(0,1) scalar or vector of length equal to the CRC length, specifying the initial state of the internal shift register. The default value is 0.

Direct method
  • When checked, the block uses the direct algorithm for CRC checksum calculations.

  • When unchecked, the block uses the non-direct algorithm for CRC checksum calculations.

The default value is unchecked.

Refer to Cyclic Redundancy Check Codes to learn about the direct and non-direct algorithms.

Reflect input
  • The input data width must be a multiple of 8.

  • When checked, each input byte is flipped before entering the shift register.

  • When unchecked, the message data is passed to the shift register unchanged.

The default value is unchecked.

Reflect CRC checksum
  • The CRC length must be a multiple of 8.

  • When checked, each checksum byte is flipped before it is passed to the final XOR stage.

  • When unchecked, the checksum byte is passed to the final XOR stage unchanged.

The default value is unchecked.

Final XOR value

The value with which the CRC checksum is to be XORed just prior to being appended to the input data. A double, boolean, or fixdt(0,1) scalar or vector of length equal to the CRC length, specifying the FinalXOR value. The default value is 0.

Simulate using

Type of simulation to run. This parameter does not affect generated HDL code.

  • Code generation (default)

    Simulate model using generated C code. The first time you run a simulation, Simulink® generates C code for the block. The C code is reused for subsequent simulations, as long as the model does not change. This option requires additional startup time but provides faster simulation speed than Interpreted execution.

  • Interpreted execution

    Simulate model using the MATLAB® interpreter. This option shortens startup time but has slower simulation speed than Code generation.

Algorithm

Timing Diagram

Timing diagram of CRC generator

Initial Delay

The General CRC Generator HDL Optimized block introduces a latency on the output. This latency can be computed with the following equation:

initialdelay = CRC length/input data width + 2

HDL Code Generation

This block supports HDL code generation using HDL Coder™. HDL Coder provides additional configuration options that affect HDL implementation and synthesized logic. For more information on implementations, properties, and restrictions for HDL code generation, see General CRC Generator HDL Optimized in the HDL Coder documentation.

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