Decode data using a Reed-Solomon decoder
Block sublibrary of Error Correction and Detection
Reed-Solomon encoding follows the same standards as any other cyclic redundancy code. The Integer-Output RS Decoder HDL Optimized block can be used to model many communication system Forward Error Correcting (FEC) codes.
The Integer-Output RS Decoder HDL Optimized block has four input ports and six output ports (5 required, 1 optional).
|Input||Message data, one symbol at a time.||Integer or fixdt() with any binary point scaling. Doubles are allowed for simulation but not for HDL code generation.|
|Input||Indicates the start of a frame of data.||Boolean or fixdt(0,1)|
|Input||Indicates the end of a frame of data.||Boolean or fixdt(0,1)|
|Input||Indicates that input data is valid.||Boolean or fixdt(0,1)|
|Output||Message data with the checksum appended. The data width is the same as the input data port.||Same as |
|Output||Indicates the start of a frame of data.||Boolean or fixdt(0,1)|
|Output||Indicates the end of a frame of data, including checksum.||Boolean or fixdt(0,1)|
|Output||Indicates that output data is valid.||Boolean or fixdt(0,1)|
|Output||Indicates the corruption of the received data when error is high.||Boolean|
|Output (optional)||Count of detected errors.||uint8|
The length of the code word
be less than
2^16-1. The number of parity symbols
be a positive even integer. A shortened code is inferred when the
number of valid data samples between
less than the codeword length. A shortened code still requires
to perform the Chien search. If the input is less than
leave guard interval of
N-size inactive cycles
before starting the next message.
The generator polynomial is not specified explicitly.
However, it is defined by the code word length, the message length,
and the B value for the starting exponent of the roots. To get the
value of B from a generator polynomial, use the
For HDL code generation, the block does not handle double-precision floating point data type numbers. You can simulate using double-precision values, but if you attempt HDL code generation, you receive an error message.
Integer-Output RS Decoder HDL Optimized Block Mask, Default View
Integer-Output RS Decoder HDL Optimized Block Mask, Expanded View
The codeword length.
The message length.
Property to enable the Primitive
Binary row vector representing the primitive polynomial in descending order of powers. When you provide a primitive polynomial, the number of input bits must be an integer multiple of K times the order of the primitive polynomial instead.
This parameter applies when only when
selected for Primitive polynomial.
Property to enable the B
The starting exponent of the roots.
This field is available only when you select
Property for Source
of B, the starting power for roots of the primitive polynomial.
Check this box to enable the
port. This port outputs the detected error count.
Type of simulation to run. This parameter does not affect generated HDL code.
Code generation (default)
Simulate model using generated C code. The first time you run
a simulation, Simulink® generates C code for the block. The C
code is reused for subsequent simulations, as long as the model does
not change. This option requires additional startup time but provides
faster simulation speed than
Simulate model using the MATLAB® interpreter. This option
shortens startup time but has slower simulation speed than
This block supports HDL code generation using HDL Coder™. HDL Coder provides additional configuration options that affect HDL implementation and synthesized logic. For more information on implementations, properties, and restrictions for HDL code generation, see Integer-Output RS Decoder HDL Optimized in the HDL Coder documentation.