Decode data using a Reed-Solomon decoder

Block sublibrary of Error Correction and Detection

Reed-Solomon encoding follows the same standards as any other cyclic redundancy code. The Integer-Output RS Decoder HDL Optimized block can be used to model many communication system Forward Error Correcting (FEC) codes.

For more about the Reed-Solomon decoder, see the Integer-Output RS Decoder block reference. For more information on representing data for Reed-Solomon codes, see Integer Format (Reed-Solomon Only).

The Integer-Output RS Decoder HDL Optimized block has four input ports and six output ports (5 required, 1 optional).

Port | Direction | Description | Data Type |
---|---|---|---|

`datain` | Input | Message data, one symbol at a time. | Integer or fixdt() with any binary point scaling. Doubles are allowed for simulation but not for HDL code generation. |

`start` | Input | Indicates the start of a frame of data. | Boolean or fixdt(0,1) |

`end` | Input | Indicates the end of a frame of data. | Boolean or fixdt(0,1) |

`valid` | Input | Indicates that input data is valid. | Boolean or fixdt(0,1) |

`dataout` | Output | Message data with the checksum appended. The data width is the same as the input data port. | Same as `datain` |

`startout` | Output | Indicates the start of a frame of data. | Boolean or fixdt(0,1) |

`endout` | Output | Indicates the end of a frame of data, including checksum. | Boolean or fixdt(0,1) |

`validout` | Output | Indicates that output data is valid. | Boolean or fixdt(0,1) |

`err` | Output | Indicates the corruption of the received data when error is high. | Boolean |

`numerrs` | Output (optional) | Count of detected errors. | uint8 |

The length of the code word

`N`

must be less than`2^16-1`

. The number of parity symbols`N-K`

must be a positive even integer. A shortened code is inferred when the number of valid data samples between`start`

and`end`

is less than the codeword length. A shortened code still requires`N`

cycles to perform the Chien search. If the input is less than`N`

symbols, leave guard interval of`N-size`

inactive cycles before starting the next message.The generator polynomial is not specified explicitly. However, it is defined by the code word length, the message length, and the B value for the starting exponent of the roots. To get the value of B from a generator polynomial, use the

`genpoly2b`

function.For HDL code generation, the block does not handle double-precision floating point data type numbers. You can simulate using double-precision values, but if you attempt HDL code generation, you receive an error message.

** Integer-Output RS Decoder HDL
Optimized Block Mask, Default View**

** Integer-Output RS Decoder HDL
Optimized Block Mask, Expanded View**

**Codeword length**The codeword length.

**Message length**The message length.

**Source of primitive polynomial**Select

`Property`

to enable the**Primitive polynomial**parameter.**Primitive polynomial**Binary row vector representing the primitive polynomial in descending order of powers. When you provide a primitive polynomial, the number of input bits must be an integer multiple of

*K*times the order of the primitive polynomial instead.This parameter applies when only when

`Property`

is selected for**Primitive polynomial**.**Source of B, the starting power for roots of the primitive polynomial**Select

`Property`

to enable the**B value**parameter.**B value**The starting exponent of the roots.

This field is available only when you select

`Property`

for**Source of B, the starting power for roots of the primitive polynomial**.**Enable number of errors output**Check this box to enable the

`numerrs`

output port. This port outputs the detected error count.**Simulate using**Type of simulation to run. This parameter does not affect generated HDL code.

`Code generation`

(default)Simulate model using generated C code. The first time you run a simulation, Simulink

^{®}generates C code for the block. The C code is reused for subsequent simulations, as long as the model does not change. This option requires additional startup time but provides faster simulation speed than`Interpreted execution`

.`Interpreted execution`

Simulate model using the MATLAB

^{®}interpreter. This option shortens startup time but has slower simulation speed than`Code generation`

.

This block supports HDL code generation using HDL Coder™. HDL Coder provides additional configuration options that affect HDL implementation and synthesized logic. For more information on implementations, properties, and restrictions for HDL code generation, see Integer-Output RS Decoder HDL Optimized in the HDL Coder documentation.

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