Generate pseudonoise sequence
Sequence Generators sublibrary of Comm Sources
The PN Sequence Generator block generates a sequence of pseudorandom binary numbers using a linear-feedback shift register (LFSR). This block implements LFSR using a simple shift register generator (SSRG, or Fibonacci) configuration. A pseudonoise sequence can be used in a pseudorandom scrambler and descrambler. It can also be used in a direct-sequence spread-spectrum system.
This block can output sequences that vary in length during simulation. For more information about variable-size signals, see Variable-Size Signal Basics in the Simulink® documentation.
The PN Sequence Generator block uses a shift register to generate sequences, as shown below.
All r registers in the generator update their values at each time step, according to the value of the incoming arrow to the shift register. The adders perform addition modulo 2. The shift register is described by the Generator Polynomial parameter, which is a primitive binary polynomial in z, grzr+gr-1zr-1+gr-2zr-2+...+g0. The coefficient gk is 1 if there is a connection from the kth register, as labeled in the preceding diagram, to the adder. The leading term gr and the constant term g0 of the Generator Polynomial parameter must be 1 because the polynomial must be primitive.
You can specify the Generator polynomial parameter using either of these formats:
A vector that lists the coefficients of the polynomial in descending order of powers. The first and last entries must be 1. Note that the length of this vector is one more than the degree of the generator polynomial.
A vector containing the exponents of z for
the nonzero terms of the polynomial in descending order of powers.
The last entry must be
[1 0 0 0 0 0 1 0 1] and
2 0] represent the same polynomial, p(z) = z8 +
z2 + 1.
The Initial states parameter is a vector specifying the initial values of the registers. The Initial states parameter must satisfy these criteria:
All elements of the Initial states vector must be binary numbers.
The length of the Initial states vector must equal the degree of the generator polynomial.
Note At least one element of the Initial states vector must be nonzero in order for the block to generate a nonzero sequence. That is, the initial state of at least one of the registers must be nonzero.
For example, the following table indicates two sets of parameter values that correspond to a generator polynomial of p(z) = z8 + z2 + 1.
|Quantity||Example 1||Example 2|
|Degree of generator polynomial||8, which is ||8|
Output mask vector (or scalar shift value) shifts the starting point of the output sequence. With the default setting for this parameter, the only connection is along the arrow labeled m0, which corresponds to a shift of 0. The parameter is described in greater detail below.
You can shift the starting point of the PN sequence with Output mask vector (or scalar shift value). You can specify the parameter in either of two ways:
An integer representing the length of the shift
A binary vector, called the mask vector, whose length is equal to the degree of the generator polynomial
The difference between the block's output when you set Output mask vector (or scalar shift value) to 0, versus a positive integer d, is shown in the following table.
|T = 0||T = 1||T = 2||...||T = d||T = d+1|
|Shift = 0||x0||x1||x2||...||xd||xd+1|
|Shift = d||xd||xd+1||xd+2||...||x2d||x2d+1|
Alternatively, you can set Output mask vector (or
scalar shift value) to a binary vector, corresponding to
a polynomial in z, mr-1zr-1 +
mr-2zr-2 + ... +
m1z + m0, of degree
at most r-1. The mask vector corresponding to a shift of d is the
vector that represents m(z) = zd modulo
g(z), where g(z) is the
generator polynomial. For example, if the degree of the generator
polynomial is 4, then the mask vector corresponding to d = 2 is
1 0 0], which represents the polynomial m(z) = z2.
The preceding schematic diagram shows how Output mask vector
(or scalar shift value) is implemented when you specify
it as a mask vector. The default setting for Output mask
vector (or scalar shift value) is
You can calculate the mask vector using the Communications System Toolbox™ function
You can use an external signal to reset the values of the internal shift register to the initial state by selecting Reset on nonzero input. This creates an input port for the external signal in the PN Sequence Generator block. The way the block resets the internal shift register depends on whether its output signal and the reset signal are sample-based or frame-based. The following example demonstrates the possible alternatives.
Suppose that the PN Sequence Generator block outputs
0 0 1 1 0 1 1] when there is no reset. You then select Reset
on nonzero input and input a reset signal [0 0 0 1]. The
following table shows three possibilities for the properties of the
reset signal and the PN Sequence Generator block.
|Reset Signal Properties||PN Sequence Generator block||Reset Signal, Output Signal|
Sample time = 1
Sample time = 1
Sample time =1
Samples per frame = 2
Sample time = 1
Samples per frame = 2
Sample time = 2
Samples per frame = 1
Sample time = 1
Samples per frame = 2
In the first two cases, the PN sequence is reset at the fourth bit, because the fourth bit of the reset signal is a 1 and the Sample time is 1. Note that in the second case, the frame sizes are 2, and the reset occurs at the end of the second frame.
In the third case, the PN sequence is reset at the seventh bit. This is because the reset signal has Sample time 2, so the reset bit is first sampled at the seventh bit. With these settings, the reset always occurs at the beginning of a frame.
If the Frame-based outputs box is selected, the output signal is a frame-based column vector whose length is the Samples per frame parameter. Otherwise, the output signal is a one-dimensional scalar.
If you want to generate a sequence of the maximum possible length for a fixed degree, r, of the generator polynomial, you can set Generator polynomial to a value from the following table. See  for more information about the shift-register configurations that these polynomials represent.
|r||Generator Polynomial||r||Generator Polynomial|
|18||37||[37 12 10 2 0]|
|19||38||[38 6 5 1 0]|
|20||39||[39 8 0]|
|40||47||[47 14 0]|
|41||48||[48 28 27 1 0]|
|42||49||[49 9 0]|
|43||50||[50 4 3 2 0]|
|44||51||[51 6 3 1 0]|
|45||52||[52 3 0]|
|46||53||[53 6 2 1 0]|
This example clarifies the operation of the
Generator block by comparing the output sequence from the
library block with that generated from primitive Simulink blocks.
For the chosen generator polynomial, , the model generates a PN sequence of period 63, using both the library block and corresponding Simulink blocks. It shows how the two parameters, Initial states and Output mask vector (or scalar shift value), are interpreted in the latter schematic.
You can experiment with different initial states, by changing the value of Initial states prior to running the simulation. For all values, the two generated sequences are the same.
Using the PN Sequence Generator block allows you to easily generate PN sequences of large periods.
Polynomial that determines the shift register's feedback connections.
Vector of initial states of the shift registers.
Specifies how output mask information is given to the block.
When you set this parameter to
parameter, the field Output mask vector (or
scalar shift value) is enabled for user input.
When set this parameter to
Mask input port appears on the block icon. The
port only accepts mask vectors.
This field is available only when Output mask source is
Integer scalar or binary vector that determines the delay of the PN sequence from the initial time. If you specify the shift as a binary vector, the vector's length must equal the degree of the generator polynomial.
Select this check box if you want the output sequences to vary in length during simulation. The default selection outputs fixed-length signals.
Specify how the block defines maximum output size for a signal.
When you select
the value you enter in the Maximum output size parameter
specifies the maximum size of the output. When you make this selection,
oSiz input port specifies the current size
of the output signal and the block output inherits sample time from
the input signal. The input value must be less than or equal to the Maximum
output size parameter.
When you select
Inherit from reference
port, the block output inherits sample time, maximum
size, and current size from the variable-sized signal at the Ref input
This parameter only appears when you select Output
variable-size signals. The default selection is
Specify a two-element row vector denoting the maximum output
size for the block. The second element of the vector must be
example, [10 1] gives a 10-by-1 maximum sized output signal. This
parameter only appears when you select Output variable-size
Period of each element of the output signal.
Determines whether the output is frame-based or sample-based.
The number of samples in a frame-based output signal. This field is active only if you select Frame-based outputs.
When selected, you can specify an input signal that resets the internal shift registers to the original values of the Initial states parameter.
When selected, the field Number of packed bits and the option Interpret bit-packed values as signed is enabled.
Indicates how many bits to pack into each output data word (allowable range is 1 to 32).
Indicates whether packed bits are treated as signed or unsigned integer data values. When selected, a 1 in the most significant bit (sign bit) indicates a negative value.
By default, this is set to
When Enable bit-packed outputs is not selected,
the output data type can be specified as a
Smallest unsigned integer. When the parameter
is set to
Smallest unsigned integer, the output
data type is selected based on the settings used in the Hardware
Implementation pane of the Configuration Parameters dialog
box of the model. If
ASIC/FPGA is selected in the Hardware
Implementation pane, the output data type is the ideal
minimum one-bit size, i.e.,
ufix(1). For all other
selections, it is an unsigned integer with the smallest available
word length large enough to fit one bit, usually corresponding to
the size of a char (e.g.,
When Enable bit-packed outputs is selected,
the output data type can be specified as
integer. When the parameter is set to
integer, the output data type is selected based on Interpret
bit-packed values as signed, Number of packed
bits, and the settings used in the Hardware Implementation pane
of the Configuration Parameters dialog box of the model. If
selected in the Hardware Implementation pane,
the output data type is the ideal minimum
based on Interpret bit-packed values as signed.
For all other selections, it is a signed or unsigned integer with
the smallest available word length large enough to fit
This example model considers pseudo-random spreading for a single-user system in a multipath transmission environment.
modelname = 'pn_sequence_block_example1'; open_system(modelname); sim(modelname);
In this case for a three path channel, there are gains due to diversity combining. This is made possible by the ideal auto-correlation properties of the PN sequences used.
To experiment with this model further, change the PN Sequence Generator block parameters. Additionally for the same sequences,select other path delays to see performance variations.
This model considers pseudo-random spreading for a combined two-user transmission in a multipath environment.
modelname = 'pn_sequence_block_example2'; open_system(modelname); sim(modelname);
For the two distinct PN sequences used for spreading, note that the individual user performance has now worsened for the same channel conditions (compare 139 errors to 41 from above). This is primarily due to the higher cross-correlation values between the two sequences which prevent ideal separation. Note, there are still advantages to combining as the error rate for a multipath plus AWGN channel with RAKE combining is nearly as good as for an AWGN-only case.
This block supports HDL code generation using HDL Coder™. HDL Coder provides additional configuration options that affect HDL implementation and synthesized logic. For more information on implementations, properties, and restrictions for HDL code generation, see PN Sequence Generator in the HDL Coder documentation.
 Proakis, John G., Digital Communications, Third edition, New York, McGraw Hill, 1995.
 Lee, J. S., and L. E. Miller, CDMA Systems Engineering Handbook, Artech House, 1998.
 Golomb, S.W., Shift Register Sequences, Aegean Park Press, 1967.