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# PN Sequence Generator

Generate pseudonoise sequence

## Library

Sequence Generators sublibrary of Comm Sources

## Description

The PN Sequence Generator block generates a sequence of pseudorandom binary numbers using a linear-feedback shift register (LFSR). This block implements LFSR using a simple shift register generator (SSRG, or Fibonacci) configuration. A pseudonoise sequence can be used in a pseudorandom scrambler and descrambler. It can also be used in a direct-sequence spread-spectrum system.

This block can output sequences that vary in length during simulation. For more information about variable-size signals, see Variable-Size Signal Basics in the Simulink® documentation.

The PN Sequence Generator block uses a shift register to generate sequences, as shown below.

All r registers in the generator update their values at each time step, according to the value of the incoming arrow to the shift register. The adders perform addition modulo 2. The shift register is described by the Generator Polynomial parameter, which is a primitive binary polynomial in z, grzr+gr-1zr-1+gr-2zr-2+...+g0. The coefficient gk is 1 if there is a connection from the kth register, as labeled in the preceding diagram, to the adder. The leading term gr and the constant term g0 of the Generator Polynomial parameter must be 1 because the polynomial must be primitive.

You can specify the Generator polynomial parameter using either of these formats:

• A vector that lists the coefficients of the polynomial in descending order of powers. The first and last entries must be 1. Note that the length of this vector is one more than the degree of the generator polynomial.

• A vector containing the exponents of z for the nonzero terms of the polynomial in descending order of powers. The last entry must be 0.

For example, [1 0 0 0 0 0 1 0 1] and [8 2 0] represent the same polynomial, p(z) = z8 + z2 + 1.

The Initial states parameter is a vector specifying the initial values of the registers. The Initial states parameter must satisfy these criteria:

• All elements of the Initial states vector must be binary numbers.

• The length of the Initial states vector must equal the degree of the generator polynomial.

 Note   At least one element of the Initial states vector must be nonzero in order for the block to generate a nonzero sequence. That is, the initial state of at least one of the registers must be nonzero.

For example, the following table indicates two sets of parameter values that correspond to a generator polynomial of p(z) = z8 + z2 + 1.

QuantityExample 1Example 2
Generator polynomialg1 = [1 0 0 0 0 0 1 0 1]g2 = [8 2 0]
Degree of generator polynomial 8, which is length(g1)-18
Initial states[1 0 0 0 0 0 1 0][1 0 0 0 0 0 1 0]

Output mask vector (or scalar shift value) shifts the starting point of the output sequence. With the default setting for this parameter, the only connection is along the arrow labeled m0, which corresponds to a shift of 0. The parameter is described in greater detail below.

You can shift the starting point of the PN sequence with Output mask vector (or scalar shift value). You can specify the parameter in either of two ways:

• An integer representing the length of the shift

• A binary vector, called the mask vector, whose length is equal to the degree of the generator polynomial

The difference between the block's output when you set Output mask vector (or scalar shift value) to 0, versus a positive integer d, is shown in the following table.

T = 0 T = 1 T = 2 ... T = d T = d+1
Shift = 0 x0x1x2... xdxd+1
Shift = d xdxd+1xd+2... x2dx2d+1

Alternatively, you can set Output mask vector (or scalar shift value) to a binary vector, corresponding to a polynomial in z, mr-1zr-1 + mr-2zr-2 + ... + m1z + m0, of degree at most r-1. The mask vector corresponding to a shift of d is the vector that represents m(z) = zd modulo g(z), where g(z) is the generator polynomial. For example, if the degree of the generator polynomial is 4, then the mask vector corresponding to d = 2 is [0 1 0 0], which represents the polynomial m(z) = z2. The preceding schematic diagram shows how Output mask vector (or scalar shift value) is implemented when you specify it as a mask vector. The default setting for Output mask vector (or scalar shift value) is 0. You can calculate the mask vector using the Communications System Toolbox™ function shift2mask.

You can use an external signal to reset the values of the internal shift register to the initial state by selecting Reset on nonzero input. This creates an input port for the external signal in the PN Sequence Generator block. The way the block resets the internal shift register depends on whether its output signal and the reset signal are sample-based or frame-based. The following example demonstrates the possible alternatives.

### Example: Resetting a Signal

Suppose that the PN Sequence Generator block outputs [1 0 0 1 1 0 1 1] when there is no reset. You then select Reset on nonzero input and input a reset signal [0 0 0 1]. The following table shows three possibilities for the properties of the reset signal and the PN Sequence Generator block.

Reset Signal PropertiesPN Sequence Generator block Reset Signal, Output Signal

Sample-based

Sample time = 1

Sample-based

Sample time = 1

Frame-based

Sample time =1

Samples per frame = 2

Frame-based

Sample time = 1

Samples per frame = 2

Sample-based

Sample time = 2

Samples per frame = 1

Frame-based

Sample time = 1

Samples per frame = 2

In the first two cases, the PN sequence is reset at the fourth bit, because the fourth bit of the reset signal is a 1 and the Sample time is 1. Note that in the second case, the frame sizes are 2, and the reset occurs at the end of the second frame.

In the third case, the PN sequence is reset at the seventh bit. This is because the reset signal has Sample time 2, so the reset bit is first sampled at the seventh bit. With these settings, the reset always occurs at the beginning of a frame.

### Attributes of Output Signal

If the Frame-based outputs box is selected, the output signal is a frame-based column vector whose length is the Samples per frame parameter. Otherwise, the output signal is a one-dimensional scalar.

### Sequences of Maximum Length

If you want to generate a sequence of the maximum possible length for a fixed degree, r, of the generator polynomial, you can set Generator polynomial to a value from the following table. See [1] for more information about the shift-register configurations that these polynomials represent.

rGenerator PolynomialrGenerator Polynomial
2 [2 1 0]21 [21 19 0]
3 [3 2 0]22 [22 21 0]
4 [4 3 0]23 [23 18 0]
5 [5 3 0]24 [24 23 22 17 0]
6 [6 5 0]25 [25 22 0]
7 [7 6 0]26 [26 25 24 20 0]
8 [8 6 5 4 0]27 [27 26 25 22 0]
9 [9 5 0]28 [28 25 0]
10 [10 7 0]29 [29 27 0]
11 [11 9 0]30 [30 29 28 7 0]
12 [12 11 8 6 0]31 [31 28 0]
13 [13 12 10 9 0]32 [32 31 30 10 0]
14 [14 13 8 4 0]33 [33 20 0]
15 [15 14 0]34 [34 15 14 1 0]
16 [16 15 13 4 0]35 [35 2 0]
17 [17 14 0]36 [36 11 0]
18 [18 11 0]37 [37 12 10 2 0]
19 [19 18 17 14 0]38 [38 6 5 1 0]
20 [20 17 0]39 [39 8 0]
40 [40 5 4 3 0]47 [47 14 0]
41 [41 3 0]48 [48 28 27 1 0]
42 [42 23 22 1 0]49 [49 9 0]
43 [43 6 4 3 0]50 [50 4 3 2 0]
44 [44 6 5 2 0]51 [51 6 3 1 0]
45 [45 4 3 1 0]52 [52 3 0]
46 [46 21 10 1 0]53 [53 6 2 1 0]

### Example of PN Sequence Generation

This example clarifies the operation of the PN Sequence Generator block by comparing the output sequence from the library block with that generated from primitive Simulink blocks.

To open the modelopen the model, enter doc_pnseq2 at the MATLAB® command line.

For the chosen generator polynomial, $p\left(z\right)={z}^{6}+z+1$, the model generates a PN sequence of period 63, using both the library block and corresponding Simulink blocks. It shows how the two parameters, Initial states and Output mask vector (or scalar shift value), are interpreted in the latter schematic.

You can experiment with different initial states, by changing the value of Initial states prior to running the simulation. For all values, the two generated sequences are the same.

Using the PN Sequence Generator block allows you to easily generate PN sequences of large periods.

## Dialog Box

Generator polynomial

Polynomial that determines the shift register's feedback connections.

Initial states

Vector of initial states of the shift registers.

Specifies how output mask information is given to the block.

• When you set this parameter to Dialog parameter, the field Output mask vector (or scalar shift value) is enabled for user input.

• When set this parameter to Input port, a Mask input port appears on the block icon. The Mask input port only accepts mask vectors.

Output mask vector (or scalar shift value)

This field is available only when Output mask source is set to Dialog parameter.

Integer scalar or binary vector that determines the delay of the PN sequence from the initial time. If you specify the shift as a binary vector, the vector's length must equal the degree of the generator polynomial.

Output variable-size signals

Select this check box if you want the output sequences to vary in length during simulation. The default selection outputs fixed-length signals.

Maximum output size source

Specify how the block defines maximum output size for a signal.

• When you select Dialog parameter, the value you enter in the Maximum output size parameter specifies the maximum size of the output. When you make this selection, the oSiz input port specifies the current size of the output signal and the block output inherits sample time from the input signal. The input value must be less than or equal to the Maximum output size parameter.

• When you select Inherit from reference port, the block output inherits sample time, maximum size, and current size from the variable-sized signal at the Ref input port.

This parameter only appears when you select Output variable-size signals. The default selection is Dialog parameter.

Maximum output size

Specify a two-element row vector denoting the maximum output size for the block. The second element of the vector must be 1 For example, [10 1] gives a 10-by-1 maximum sized output signal. This parameter only appears when you select Output variable-size signals.

Sample time

Period of each element of the output signal.

Frame-based outputs

Determines whether the output is frame-based or sample-based.

Samples per frame

The number of samples in a frame-based output signal. This field is active only if you select Frame-based outputs.

Reset on nonzero input

When selected, you can specify an input signal that resets the internal shift registers to the original values of the Initial states parameter.

Enable bit-packed outputs

When selected, the field Number of packed bits and the option Interpret bit-packed values as signed is enabled.

Number of packed bits

Indicates how many bits to pack into each output data word (allowable range is 1 to 32).

Interpret bit-packed values as signed

Indicates whether packed bits are treated as signed or unsigned integer data values. When selected, a 1 in the most significant bit (sign bit) indicates a negative value.

Output data type

By default, this is set to double.

When Enable bit-packed outputs is not selected, the output data type can be specified as a double, boolean, or Smallest unsigned integer. When the parameter is set to Smallest unsigned integer, the output data type is selected based on the settings used in the Hardware Implementation pane of the Configuration Parameters dialog box of the model. If ASIC/FPGA is selected in the Hardware Implementation pane, the output data type is the ideal minimum one-bit size, i.e., ufix(1). For all other selections, it is an unsigned integer with the smallest available word length large enough to fit one bit, usually corresponding to the size of a char (e.g., uint8).

When Enable bit-packed outputs is selected, the output data type can be specified as double or Smallest integer. When the parameter is set to Smallest integer, the output data type is selected based on Interpret bit-packed values as signed, Number of packed bits, and the settings used in the Hardware Implementation pane of the Configuration Parameters dialog box of the model. If ASIC/FPGA is selected in the Hardware Implementation pane, the output data type is the ideal minimum n-bit size, i.e., sfix(n) or ufix(n), based on Interpret bit-packed values as signed. For all other selections, it is a signed or unsigned integer with the smallest available word length large enough to fit n bits.

## Examples

This example model considers pseudo-random spreading for a single-user system in a multipath transmission environment.

Open the model here: pn_sequence_block_example1pn_sequence_block_example1

```modelname = 'pn_sequence_block_example1';
open_system(modelname);
sim(modelname);```

In this case for a three path channel, there are gains due to diversity combining. This is made possible by the ideal auto-correlation properties of the PN sequences used.

To experiment with this model further, change the PN Sequence Generator block parameters. Additionally for the same sequences,select other path delays to see performance variations.

`close_system(modelname, 0);`

### PN Spreading with Two Users and Multipath

This model considers pseudo-random spreading for a combined two-user transmission in a multipath environment.

Open the model here: pn_sequence_block_example2pn_sequence_block_example2

```modelname = 'pn_sequence_block_example2';
open_system(modelname);
sim(modelname);```

For the two distinct PN sequences used for spreading, note that the individual user performance has now worsened for the same channel conditions (compare 139 errors to 41 from above). This is primarily due to the higher cross-correlation values between the two sequences which prevent ideal separation. Note, there are still advantages to combining as the error rate for a multipath plus AWGN channel with RAKE combining is nearly as good as for an AWGN-only case.

`close_system(modelname, 0);`

## HDL Code Generation

This block supports HDL code generation using HDL Coder™. HDL Coder provides additional configuration options that affect HDL implementation and synthesized logic. For more information on implementations, properties, and restrictions for HDL code generation, see PN Sequence Generator in the HDL Coder documentation.