Documentation 
The Rectangular QAM Demodulator Baseband block demodulates a signal that was modulated using quadrature amplitude modulation with a constellation on a rectangular lattice.
The signal constellation has M points, where M is the Mary number parameter. M must have the form 2^{K} for some positive integer K. The block scales the signal constellation based on how you set the Normalization method parameter. For details, see the reference page for the Rectangular QAM Modulator Baseband block.
This block accepts a scalar or column vector input signal. For information about the data types each block port supports, see the Supported Data Types table on this page.
The demodulator algorithm maps received input signal constellation values to Mary integer I and Q symbol indices between 0 and $$\sqrt{\text{M}}1$$ and then maps these demodulated symbol indices to formatted output values.
The integer symbol index computation is performed by first derotating and scaling the complex input signal constellation (possibly with noise) by a derotate factor and denormalization factor, respectively. These factors are derived from the Phase offset, Normalization method, and related parameters. These derotated and denormalized values are added to $$\sqrt{\text{M}}1$$ to translate them into an approximate range between 0 and $$2\times (\sqrt{\text{M}}1)$$ (plus noise). The resulting values are then rescaled via a dividebytwo (or, equivalently, a rightshift by one bit for fixedpoint operation) to obtain a range approximately between 0 and $$\sqrt{\text{M}}1$$ (plus noise) for I and Q. The noisy index values are rounded to the nearest integer and clipped, via saturation, and mapped to integer symbol values in the range [0 M1]. Finally, based on other block parameters, the integer index is mapped to a symbol value that is formatted and cast to the selected Output data type.
The following figures contains signal flow diagrams for floatingpoint and fixedpoint algorithm operation. The floatingpoint diagrams apply when the input signal data type is double or single. The fixedpoint diagrams apply when the input signal is a signed fixedpoint data type. Note that the diagram is simplified when Phase offset is a multiple of $$\frac{\pi}{2}$$, and/or the derived denormalization factor is 1.
SignalFlow Diagrams with Trivial Phase Offset and Denormalization Factor Equal to 1
SignalFlow Diagrams with Nontrivial Phase Offset and Nonunity Denormalization Factor
The number of points in the signal constellation. It must have the form 2^{K} for some positive integer K.
Determines how the block scales the signal constellation. Choices are Min. distance between symbols, Average Power, and Peak Power.
This parameter appears when Normalization method is set to Min. distance between symbols.
The distance between two nearest constellation points.
The average power of the symbols in the constellation, referenced to 1 ohm. This field appears only when Normalization method is set to Average Power.
The maximum power of the symbols in the constellation, referenced to 1 ohm. This field appears only when Normalization method is set to Peak Power.
The rotation of the signal constellation, in radians.
Determines how the block assigns binary words to points of the signal constellation. More details are on the reference page for the Rectangular QAM Modulator Baseband block.
Selecting Userdefined displays the field Constellation mapping, allowing for userspecified mapping.
This parameter appears when Userdefined is selected in the pulldown list Constellation ordering.
This is a row or column vector of size M and must have unique integer values in the range [0, M1]. The values must be of data type double.
The first element of this vector corresponds to the topleftmost point of the constellation, with subsequent elements running down columnwise, from left to right. The last element corresponds to the bottomrightmost point.
Determines whether the block produces integers or binary representations of integers.
If set to Integer, the block produces integers.
If set to Bit, the block produces a group of K bits, called a binary word, for each symbol, when Decision type is set to Hard decision. If Decision type is set to Loglikelihood ratio or Approximate loglikelihood ratio, the block outputs bitwise LLR and approximate LLR, respectively.
This parameter appears when Bit is selected in the pulldown list Output type.
Specifies the use of hard decision, LLR, or approximate LLR during demodulation. See Exact LLR Algorithm and Approximate LLR Algorithm in the Communications System Toolbox™ User's Guide for algorithm details.
This parameter appears when Approximate loglikelihood ratio or Loglikelihood ratio is selected for Decision type.
When set to Dialog, the noise variance can be specified in the Noise variance field. When set to Port, a port appears on the block through which the noise variance can be input.
This parameter appears when the Noise variance source is set to Dialog and specifies the noise variance in the input signal. This parameter is tunable in normal mode, Accelerator mode and Rapid Accelerator mode.
If you use the Simulink^{®} Coder™ rapid simulation (RSIM) target to build an RSIM executable, then you can tune the parameter without recompiling the model. This is useful for Monte Carlo simulations in which you run the simulation multiple times (perhaps on multiple computers) with different amounts of noise.
The LLR algorithm involves computing exponentials of very large or very small numbers using finite precision arithmetic and would yield:
Inf to Inf if Noise variance is very high
NaN if Noise variance and signal power are both very small
In such cases, use approximate LLR, as its algorithm does not involve computing exponentials.
When the parameter is set to 'Inherit via internal rule' (default setting), the block will inherit the output data type from the input port. The output data type will be the same as the input data type if the input is of type single or double. Otherwise, the output data type will be as if this parameter is set to 'Smallest unsigned integer'.
When the parameter is set to 'Smallest unsigned integer', the output data type is selected based on the settings used in the Hardware Implementation pane of the Configuration Parameters dialog box of the model. If ASIC/FPGA is selected in the Hardware Implementation pane, the output data type is the ideal minimum size, i.e., ufix(1) for bit outputs, and ufix(ceil(log2(M))) for integer outputs. For all other selections, it is an unsigned integer with the smallest available word length large enough to fit the ideal minimum size, usually corresponding to the size of a char (e.g., uint8).
For integer outputs, this parameter can be set to Smallest unsigned integer, int8, uint8, int16, uint16, int32, uint32, single, and double. For bit outputs, the options are Smallest unsigned integer, int8, uint8, int16, uint16, int32, uint32, boolean, single, or double.
This parameter only applies when the input is fixedpoint and Phase offset is not a multiple of $$\frac{\pi}{2}$$.
This can be set to Same word length as input or Specify word length, in which case a field is enabled for user input.
This parameter only applies when the input is fixedpoint and the derived denormalization factor is nonunity (not equal to 1). This scaling factor is derived from Normalization method and other parameter values in the block dialog.
This can be set to Same word length as input or Specify word length, in which case a field is enabled for user input. A bestprecision fraction length is always used.
This parameter only applies when the input is a fixedpoint signal and there is a nonunity (not equal to 1) denormalized factor. It can be set to Inherit via internal rule or Specify word length, which enables a field for user input.
Setting to Inherit via internal rule computes the fullprecision product word length and fraction length. Internal Rule for Product Data Types in DSP System Toolbox™ User's Guide describes the fullprecision Product output internal rule.
Setting to Specify word length allows you to define the word length. The block computes a bestprecision fraction length based on the word length specified and the precomputed worstcase (min/max) real world value Product output result. The worstcase Product output result is precomputed by multiplying the denormalized factor with the worstcase (min/max) input signal range, purely based on the input signal data type.
The block uses the Rounding mode when the result of a fixedpoint calculation does not map exactly to a number representable by the data type and scaling storing the result. For more information, see Rounding Modes in the DSP System Toolbox documentation or Rounding Mode: Simplest in the FixedPoint Designer™ documentation.
This parameter only applies when the input is a fixedpoint signal. It can be set to Inherit via internal rule, Same as product output, or Specify word length, in which case a field is enabled for user input
Setting to Inherit via internal rule computes the fullprecision sum word length and fraction length, based on the two inputs to the Sum in the fixedpoint Hard Decision Algorithm signal flow diagram. The rule is the same as the fixedpoint inherit rule of the internal Accumulator data type parameter in the Simulink Sum block.
Setting to Specify word length allows you to define the word length. A best precision fraction length is computed based on the word length specified in the precomputed maximum range necessary for the demodulated algorithm to produce accurate results. The signed fixedpoint data type that has the best precision fully contains the values in the range $$2*(\sqrt{M}1)$$ for the specified word length.
Setting to Same as product output allows the Sum data type to be the same as the Product output data type (when Product output is used). If the Product output is not used, then this setting will be ignored and the Inherit via internal rule Sum setting will be used.
Port  Supported Data Types 

Input 

Var 

Output 

This block supports HDL code generation using HDL Coder™. HDL Coder provides additional configuration options that affect HDL implementation and synthesized logic. For more information on implementations, properties, and restrictions for HDL code generation, see Rectangular QAM Demodulator Baseband in the HDL Coder documentation.