Receive data from Analog Devices FMCOMMS board
The Analog Devices FMCOMMS Receiver block supports communication between Simulink® and a Xilinx® FPGA-based radio device, allowing simulation and development for various software-defined radio applications. The Analog Devices FMCOMMS Receiver block enables communication with a Xilinx FPGA board on the same Ethernet subnetwork.
The Analog Devices FMCOMMS Receiver block is a signal sink that receives data from a Xilinx FPGA board and outputs a column vector signal of fixed length. The first call to this block can contain transient values that result in packets containing undefined data.
The block diagram shows how Simulink, the Analog Devices FMCOMMS Receiver block, and Xilinx FPGA hardware interface.
When the Analog Devices FMCOMMS Receiver block is called during simulation, the host might not have received any data from the Xilinx FPGA hardware. The data length port, DataLength, indicates when valid data is present. When the data length port contains a zero value, there is no data. You can use the data length with an enabled subsystem to qualify the execution of part of the model.
If your computer is not connected to any Xilinx FPGA hardware, you can still use this block to develop a model that propagates sample time and data type information. To propagate this information, update your diagram.
The following diagram illustrates the data path for radio signal reception (when the decimation filter, IF tuner, and DC blocking filter are all in use in the block):
|Port||Supported Data Types|
The output port supports the following complex data types only:
When you select a double or single data type, the complex values are scaled to the range of [-1,1]. When you select int16, the complex values are the raw 16-bit I and Q samples from the board.
Specify the logical network location of the radio as a string. The default is 192.168.2.2 for ADI radios.
Note: If you are attaching two radios to the same host, note that each radio must be located at a different IP address. In the block mask, set the IP address for each radio to a unique value, as shown here for a pair of Analog Devices FMCOMMS Receiver and Analog Devices FMCOMMS Transmitter blocks (values shown are default for ADI FMCOMMS radios):
Configure the SDR board with chosen parameter values and read back the actual hardware values.
Choose either Dialog or Input port as the source of the center frequency value. If you choose Dialog, specify the desired center frequency as a double-precision, nonnegative, finite scalar. The default is 2.4 GHz. The valid range of values for this parameter is 400 MHz to 4 GHz.
The intermediate frequency (IF) tuner allows you to account for the error in tuning between target center frequency and actual center frequency and avoid unwanted interference by shifting it out of the pass band of interest. Choose either Dialog or Input port as the source of the center frequency value. If you choose Dialog, specify the desired center frequency as a double-precision, finite scalar. The default value is 0 Hz. The valid range of values for this parameter is to , where is the analog-digital converter (ADC) rate.
Choose either Dialog or Input port as the source of the overall gain value. If you choose Dialog, specify the gain as a double precision, nonnegative scalar. The default value and the valid range of this parameter are dependent upon the RF daughterboard. This parameter is tunable.
Specify the desired sampling rate as a double precision, nonnegative scalar. The default value is 98 MHz. The valid range of this parameter for this board is 39–100 MHz.
Specify the desired decimation factor as a double precision, nonnegative scalar. The default is 512. The baseband rate is ADC sampling rate/Decimation factor. See Decimation Factors.
Select this parameter to instruct the Analog Devices FMCOMMS Receiver block to output the number of lost samples during host-hardware data transfers.
Zero indicates no data loss.
A positive number indicates that overruns or underruns occurred.
The default value is not selected, which means that the port is not enabled and no information about dropped packets is displayed.
This port is a useful diagnostic tool to determine real-time operation of the Analog Devices FMCOMMS Receiver block. If your model is not running in real time, you can increase the decimation factor to approach or achieve real-time performance.
Specify the complex output data type as double, single, or int16. When you select double or single for the output data type, the complex values are scaled to the range of [-1,1]. When you select int16, the complex values are the raw 16–bit I and Q samples from the board. The default is int16.
This block supports the following complex output data types:
Double-precision floating point
Single-precision floating point
16-bit signed integers
Specify the sample time for a single radio sample. For the Simulink sample time to correspond to real time, use the following formula: Sample time = 1/(ADC sampling rate/Decimation factor). The default setting for this parameter is 1.
Specify a positive, scalar integer for the frame length of the output signal. Values less than 366 cany yield very poor performance. The default value is 3660.
When selected, this parameter instructs the Analog Devices FMCOMMS Receiver block to produce a set of contiguous frames without an overrun or underrun to the radio. This setting can help you simulate models that cannot run in real time. When this parameter is selected, specify the desired amount of contiguous data using the Number of frames in burst parameter. By default, this option is selected.
Specify the number of frames in contiguous burst
This parameter is valid and visible only when the Enable burst mode parameter is selected. The default number of frames in a burst is 20.
Bypass the DC bias removal filter. When you select this parameter, the DC blocking filter to automatically reduce a DC bias is bypassed. Enable this when the filter is also blocking some signal and you need to use a different DC bias compensation scheme. By default, this option is not selected, which means to include the automatic DC blocking filter.
When you select this option, the FPGA data path bypasses the algorithm generated and programmed during the SDR Targeting workflow. This bypass helps with debugging system bringup. By default, this option is not selected.
Communicate with the attached radio to obtain basic hardware information. The information appears in the Hardware Information pane.
You can verify that your Analog Devices FMCOMMS Receiver block is connected to FPGA hardware with the Info button on the block.
Open the block mask.
If the block is not connected, the panel displays the following message:
No attached SDR hardware or unable to retrieve hardware information.
The Support Package for Xilinx FPGA-Based Radio determines the radio frequency sample times using the ADC clock rate, decimation factor, and frame size, according to the following formula:
Sample time = 1/(ADC sampling rate/Decimation factor)
You can choose to use decimation to reduce your bandwidth. See Decimation FactorsDecimation Factors.
The FPGA image includes a decimation filter chain that is controlled by the Decimation Factor parameter. The filter chain consists of a CIC filter followed by two halfband filters as shown in the diagram below. The first halfband filter has a wider transition band and less filter weights than the second one. For this reason the first halfband is called Halfband Lightweight (HBL) and the second is called Halfband Heavyweight (HBH).
The filter chain supports decimation factors from the following set of values:
Any integer from 4 to 128
A multiple of 2 from 130 to 256
A multiple of 4 from 260 to 512
Note: If the desired decimation factor is not supported then it will be quantized to a supported value from the above set. Furthermore this may result in a suboptimal hardware configuration and is therefore not recommended. See the table below for examples.
The CIC filter has a variable decimation factor (CIC rate) of between 2 and 128 and may be bypassed if necessary. Each halfband filter decimates by a factor of 2 and may be also be bypassed. The filters are enabled or bypassed according to the following rules:
If the desired decimation factor is divisible by 4, then both HBL and HBH are enabled.
If the desired decimation factor is divisible by 2 and not by 4, then HBL is bypassed and HBH is enabled.
If the desired decimation factor is not divisible by 2, then HBL and HBH are both bypassed.
The remaining decimation factor is made up by the CIC filter. If the remaining factor is 1 then the CIC is bypassed.
The following table demonstrates some examples of how the filter chain is configured to implement the desired decimation factor:
|Desired Decimation Factor||CIC||HBL||HBH||Actual Decimation Factor||Recommended|
The Support Package for Xilinx FPGA-Based Radio software incorporates the logic to determine these settings automatically from the desired decimation factor block mask parameter.
Intermediate frequency (IF) tuning supports second stage tuning for both the transmit and receive data paths. The tuner is configurable at run-time (tunable), provides finer resolution when compared to the primary tuner on an RF card, and allows you to remove unwanted interference from the pass band of interest.
IF Tuning on Receive Data Path
To enable an intermediate frequency tuner, set the Intermediate Frequency parameter in the block mask for the receiver block.
Receiver Block IF Tuning
When you set block values for center frequency, intermediate frequency, ADC, gain, and decimation, the block initially performs some rudimentary checks that the values are scalar and real. If your values pass those checks, you can still provide values that are out of range for the FPGA-based radio. In that case, the hardware makes a best effort to set the requested value, and will report the actual value in the Device value column of the block mask.
The Analog Devices FMCOMMS Receiver block has an optional lost samples output port. When this port is active, it outputs a logical signal that indicates whether the block is processing data in real time. If the block is not keeping up with the hardware, the signal goes high.
This port is a useful diagnostic tool for determining real-time operation of the blocks. If your model is not running in real time, see Xilinx FPGA-Based Radio Processing Errors and Fixes.
Direct conversion receivers, such as Analog Devices FMComms1 EBZ, often impose a DC bias on the in-phase and quadrature components of the signal. DC bias, if not dealt with, leads to degraded BER performance for QAM systems, and to a lesser extent, PSK systems. With the DC blocking filter implemented in the FPGA, the DC bias is reduced in the I/Q channels of a received complex signal, to better enable robust receiver processing, and allow you to focus on designing the baseband algorithm without worrying about DC bias that is introduced by the analog front end.
The DC blocking filter is on by default. To bypass this filter, Select Bypass DC blocking filter in the Datapath Configuration section of the receiver block mask: