Transmit data to Analog Devices FMCOMMS board
The Analog Devices FMCOMMS Transmitter block supports communication between Simulink® and a Xilinx® FPGA-based radio device, allowing simulation and development for various software-defined radio applications. The Analog Devices FMCOMMS Transmitter block enables communication with a Xilinx FPGA board on the same Ethernet subnetwork.
The Analog Devices FMCOMMS Transmitter block is a Simulink source that sends data to a Xilinx FPGA board. The first call to this block may contain transient values which result in packets containing undefined data.
The following block diagram illustrates how Simulink, the Analog Devices FMCOMMS Transmitter block, and Xilinx FPGA hardware interface.
If your computer is not connected to any Xilinx FPGA hardware, you can still use the Analog Devices FMCOMMS Transmitter block to develop a model that propagates sample time and data type information. To propagate this information, select Edit > Update diagram; alternatively, you can press Ctrl + D.
The following diagram illustrates the data path for radio signal transmission (when the interpolation filter and IF tuner are specified in the block):
|Port||Supported Data Types|
The input port supports the following complex and real data types:
All input must be framed based.
When you select a double or single data type, the complex values are in the range of [-1,1] and converted to int16. When you select int16, the complex values are 16-bit I and Q samples that are then sent to the radio.
Specify the logical network location of the radio as a string. The default is 192.168.2.2 for ADI radios.
Note: If you are attaching two radios to the same host, note that each radio must be located at a different IP address. In the block mask, set the IP address for each radio to a unique value, as shown here for a pair of Analog Devices FMCOMMS Receiver and Analog Devices FMCOMMS Transmitter blocks (values shown are default for ADI FMCOMMS radios):
Configure the SDR board with chosen parameter values and reads back the actual hardware values.
Choose either Dialog or Input port as the source of the center frequency value. If you choose Dialog, specify the desired center frequency as a double-precision, nonnegative, finite scalar. The default is 2.4 Hz. The valid range of values for this parameter is 400MHz to 4GHz.
The intermediate frequency (IF) tuner allows you to account for the error in tuning between target center frequency and actual center frequency and avoid unwanted interference by shifting it out of the pass band of interest. Choose either Dialog or Input port as the source of the center frequency value. If you choose Dialog, specify the desired center frequency as a double-precision, finite scalar. The default value is 0 Hz. The valid range of values for this parameter is to , where is the digital-analog converter (DAC) rate.
Specify the desired sampling rate as a double precision, nonnegative scalar. The default value is 98MHz. The valid range of this parameter for this board is 25–125MHz.
Specify the desired interpolation factor as a double precision, nonnegative scalar. The default is 512. The baseband rate is DAC sampling rate / Interpolation factor. See Interpolation Factors.
Select this parameter to instruct the Analog Devices FMCOMMS Transmitter block to output the number of lost samples during host—hardware data transfers.
Zero indicates no data loss
A positive number indicates that overruns or underruns occurred
By default. this parameter is not selected, which means that the port is not enabled and no information about dropped packets is displayed.
This port is a useful diagnostic tool to determine real time operation of the Analog Devices FMCOMMS Transmitter block. If your model is not running in real time, you can increase the interpolation factor to approach or achieve real-time performance.
When selected, this parameter instructs the Analog Devices FMCOMMS Transmitter block to produce a set of contiguous frames without an underrun to the radio. This setting can help simulate models that cannot run in real time. When enabled, specify the desired amount of contiguous data using the Number of frames in burst parameter. By default, this parameter is not selected.
Number of frames in contiguous burst
This parameter is valid and visible only when the Enable burst mode parameter is selected. The default number of frames in a burst is 20.
When you select this option, the FPGA data path bypasses the algorithm generated and programmed during the SDR Targeting workflow. This bypass helps with debugging system bringup. By default, this option is selected.
Communicate with the attached radio to obtain basic hardware information. The information is displayed in the Hardware Information pane.
You can verify that your Analog Devices FMCOMMS Transmitter block is connected to FPGA hardware with the Info button on the block.
Open the block mask.
Click the Info button.
If the block is not connected, the panel will show the following message:
No attached SDR hardware or unable to retrieve hardware information.
When you set block values for center frequency, intermediate frequency, DAC, and interpolation, the block initially performs some rudimentary checks that the values are scalar and real. If your values pass those checks, you can still provide values that are out of range for the FPGA-based radio. In that case, the hardware will make a best effort to set the requested value, and will report the actual value in the Device value column of the block mask.
The FPGA image includes an interpolating filter chain that is controlled by the Interpolation Factor parameter. The filter chain consists of two halfband filters followed by one CIC filter as shown in the diagram below. The first halfband filter has a sharper transition band and more filter weights than the second one. For this reason the first halfband is called Halfband Heavyweight (HBH) and the second is called Halfband Lightweight (HBL).
The filter chain supports interpolation factors from the following set of values:
[5:128, 130:2:256, 260:4:512]
Any integer from 5 to 128
A multiple of 2 from 130 to 256
A multiple of 4 from 260 to 512
Note: If the desired interpolation factor is not supported then it will be quantized to a supported value from the above set. Furthermore this may result in a suboptimal hardware configuration and is therefore not recommended. See the table below for examples.
Each halfband filter interpolates by a factor of 2 and may be bypassed if necessary. The CIC filter has a variable interpolation factor (CIC rate) of between 2 and 128 and may also be bypassed. The filters are enabled or bypassed according to the following rules:
If the desired interpolation factor is divisible by 4, then both HBH and HBL are enabled.
If the desired interpolation factor is divisible by 2 and not by 4, then HBH is enabled and HBL is bypassed.
If the desired interpolation factor is not divisible by 2, then HBH and HBL are both bypassed.
The remaining interpolation factor is made up by the CIC filter. If the remaining factor is 1, then the CIC is bypassed.
|Desired Interpolation Factor||HBH||HBL||CIC||Actual Interpolation Factor||Recommended|
The Support Package for Xilinx FPGA-Based Radio software incorporates the logic to determine these settings automatically from the desired interpolation factor block mask parameter.
To enable an intermediate frequency tuner, set the Intermediate Frequency parameter in the block mask for the receiver block.
Intermediate frequency (IF) tuning supports second stage tuning for both the transmit and receive data paths. The tuner is configurable at run-time (tunable), provides finer resolution when compared to the primary tuner on an RF card, and allows you to remove unwanted interference from the pass band of interest.
IF Tuning on Transmit Data Path
To enable an intermediate frequency tuner, set the Intermediate Frequency parameter in the block mask for the transmitter block.
Transmitter Block IF Tuning
The Analog Devices FMCOMMS Transmitter block has an optional lost samples output port. When this port is active, it outputs a logical signal that indicates whether the block is processing data in real time. If the block is not keeping up with the hardware, the signal goes high.
This port is a useful diagnostic tool for determining real time operation of the blocks. If your model is not running in real time, see Xilinx FPGA-Based Radio Processing Errors and Fixes.