Receive data from Analog Devices FMCOMMS board
The SDRADIFMCOMMSReceiver System object™ receives data from a Xilinx® FPGA-based radio, allowing simulation and development for various software-defined radio applications. The SDRADIFMCOMMSReceiver object enables communication with a FPGA board on the same Ethernet subnetwork.
The SDRADIFMCOMMSReceiver System object is a signal sink that receives data from an FPGA board and outputs a column vector signal of fixed length. The first call to this object can contain transient values, which results in packets containing undefined data.
The diagram shows how MATLAB®, the SDRADIFMCOMMSReceiver System object, and Xilinx FPGA hardware interface.
The following diagram illustrates the data path for radio signal reception (when the decimation filter, IF tuner, and DC blocking filter are all specified in the object properties):
|Port||Supported Data Types|
The output port supports the following complex data types only:
When you select a double or single data type, the complex values are scaled to the range of [-1,1]. When you select int16, the complex values are the raw 16-bit I and Q samples from the board.
H = comm.SDRADIFMCOMMSReceiver creates an SDR receiver System object, H, that receives data from an FPGA development motherboard with an Analog Devices FMCOMMS daughterboard installed. The System object enables communication with an SDR board on the same gigabit Ethernet subnetwork as the host.
H = comm.SDRADIFMCOMMSReceiver(Name,Value) creates an SDR receiver System object, H, with the specified property Name set to the specified Value. You can specify additional name-value pair arguments in any order as (Name1,Value1,...,NameN,ValueN).
An SDRADIFMCOMMSReceiver System object connects to a device when you call the step method and stays connected until you call the release method.
IP address of the radio
Specify the logical network location of the radio as a string. The default is 192.168.2.2 for ADI radios.
Source of RF center frequency
Specify the source of the center frequency as Property or Input port. The default is Property. Set CenterFrequencySource to Input port to specify the center frequency value using an input to the step method. Set CenterFrequencySource to Property to specify the center frequency value using the CenterFrequency property.
RF center frequency in Hz
Specify the desired center frequency as a double-precision, nonnegative, finite scalar. This property applies when you set the CenterFrequencySource to Property.
The default is 2.4 GHz. The valid range of values for this property is 400 MHz to 4 GHz.
Actual RF center frequency in Hz
Reports the actual center frequency of the daughterboard. Desired and actual center frequency can differ slightly due to quantization. The value is NaN when the actual value is unknown. Use synchronize to update the actual value. This property is read only.
Source of RF intermediate frequency
Specify the source of the intermediate frequency as Property or Input port. The default is Property. Set IntermediateFrequencySource to Input port to specify the intermediate frequency value using an input to the step method. Set IntermediateFrequencySource to Property to specify the intermediate frequency value using the IntermediateFrequency property.
Desired intermediate frequency in Hz
The intermediate frequency (IF) tuner allows you to account for the error in tuning between target center frequency and actual center frequency and avoid unwanted interference by shifting it out of the pass band of interest. Specify the desired intermediate frequency as a double-precision, finite scalar. The default value is 0 Hz. The valid range of values for this parameter is to , where is the analog-digital converter (ADC) rate.
Actual intermediate frequency in Hz
Reports the actual intermediate frequency. Desired and actual intermediate frequency can be slightly different due to quantization. The value is NaN when the actual value is unknown. Use the synchronize method to update the actual value. This property is read-only.
Source of gain
Specify the source of the overall gain as Property or Input port. The default is Property. Set GainSource to Input port to specify the overall gain value via an input to the step method. Set GainSource to Property to specify the overall gain value via the Gain property.
Desired overall gain in dB
Specify the desired overall gain as a double-precision, nonnegative scalar. The default value and the valid range of this property depend on the RF daughterboard. This property applies when you set the GainSource to the value Property. This property is tunable.
Actual overall gain in dB
Reports the actual overall gain of the daughterboard. Desired and actual gain can differ slightly due to quantization. The value is NaN when the actual value is unknown. Use synchronize to update the actual value. This property is read only.
Desired ADC sampling rate in Hz
Specify the desired sampling rate as a double-precision, nonnegative scalar. The default value is 98 MHz. The valid range of this property is 39–100 MHz.
Actual ADC sampling rate in Hz
Reports the actual sampling rate of the RF signal. Desired and actual sampling rate can differ slightly due to quantization. The value is NaN when the actual value is unknown. Use synchronize to update the actual value. This property is read only.
Desired decimation factor
Specify the desired decimation factor as a double-precision, nonnegative scalar. The default is 512. The baseband rate is ADCRate / DecimationFactor. See Decimation Factors.
Actual decimation factor
Reports the actual decimation factor of the daughterboard. Desired and actual decimation factors can differ slightly due to quantization. The value is NaN when the actual value is unknown. Use synchronize to update the actual value. This property is read only.
Output overrun flag
Set this property to true to specify for the step method to output the number of lost samples during host—hardware data transfers.
The default value for LostSamplesOutputPort is false, which means that the port is not enabled and no information about dropped packets is displayed.
This port is a useful diagnostic tool to determine real time operation of the System object. If your design is not running in real-time, you can increase the decimation factor to approach or achieve real-time performance.
Data type of output
Specify the complex output data type as double, single, or int16. When you select double or single data type, the complex values are scaled to the range of [-1,1]. When selecting int16, the complex values are the raw 16-bit I and Q samples from the board. The default is int16.
This System object supports the following complex output data types:
Specify the frame length of the output signal that the object generates as a positive, scalar integer. Using values less than 366 can yield very poor performance. The default value is 3660.
Ensure a set of frames without overrun or underrun
When set to true, this property produces a set of contiguous frames without an overrun or underrun to the radio. This setting can help simulate models that cannot run in real time. When you enable this property, specify the desired amount of contiguous data using the NumFramesInBurst property. The default value is false.
Number of frames in contiguous burst
This property is valid when EnableBurstMode property is set to true. The default number of frames in a burst is 20.
Bypass user logic from target workflow
When you enable this property, the FPGA data path bypasses the algorithm generated and programmed during the SDR workflow. This bypass can help with debugging system bringup. The default value is false, or not enabled.
Bypass the DC bias removal filter
When true, the DC blocking filter to automatically reduce a DC bias is bypassed. Enable this when the filter is also blocking some signal and you need to use a different DC bias compensation scheme. The default is false, which means to include the automatic DC blocking filter.
|disconnect||Allow other host software to communicate with SDR board|
|info||Obtain SDR board information|
|isLocked||Locked status (logical)|
|release||Allow property value and input characteristics changes|
|step||Receive data from SDR board|
|synchronize||Configure SDR board|
Verify that your SDRADIFMCOMMSReceiver System object is connected to FPGA hardware by using the info method.
Construct an SDRADIFMCOMMSReceiver System object.
h = comm.SDRADIFMCOMMSReceiver
Use the info method:
S = info(h)
The function returns the hardware information for object h in structure S.
The System object determines the radio frequency sample times using the ADC clock rate, decimation factor, and frame size, according to the following formula: Sample time = 1/(ADCRate/DecimationFactor). You can choose to use decimation to reduce your bandwidth. See Decimation Factors.
The FPGA image includes a decimation filter chain that is controlled by the Decimation Factor parameter. The filter chain consists of a CIC filter followed by two halfband filters as shown in the diagram below. The first halfband filter has a wider transition band and less filter weights than the second one. For this reason the first halfband is called Halfband Lightweight (HBL) and the second is called Halfband Heavyweight (HBH).
The filter chain supports decimation factors from the following set of values:
Any integer from 4 to 128
A multiple of 2 from 130 to 256
A multiple of 4 from 260 to 512
Note: If the desired decimation factor is not supported then it will be quantized to a supported value from the above set. Furthermore this may result in a suboptimal hardware configuration and is therefore not recommended. See the table below for examples.
The CIC filter has a variable decimation factor (CIC rate) of between 2 and 128 and may be bypassed if necessary. Each halfband filter decimates by a factor of 2 and may be also be bypassed. The filters are enabled or bypassed according to the following rules:
If the desired decimation factor is divisible by 4, then both HBL and HBH are enabled.
If the desired decimation factor is divisible by 2 and not by 4, then HBL is bypassed and HBH is enabled.
If the desired decimation factor is not divisible by 2, then HBL and HBH are both bypassed.
The remaining decimation factor is made up by the CIC filter. If the remaining factor is 1 then the CIC is bypassed.
The following table demonstrates some examples of how the filter chain is configured to implement the desired decimation factor:
|Desired Decimation Factor||CIC||HBL||HBH||Actual Decimation Factor||Recommended|
The Support Package for Xilinx FPGA-Based Radio software incorporates the logic to determine these settings automatically from the desired Decimation factor block mask parameter.
Intermediate frequency (IF) tuning supports second stage tuning for both the transmit and receive data paths. The tuner is configurable at run-time (tunable), provides finer resolution when compared to the primary tuner on an RF card, and allows you to remove unwanted interference from the pass band of interest.
IF Tuning on Receive Data Path
To enable an intermediate frequency tuner, set the IntermediateFrequency property for the receiver System object.
rxIFValue = 1e6; so = comm.SDRADIFMCOMMSReceiver; so.IntermediateFrequency = rxIFValue
Keep in mind that the actual frequency value is stored in the property ActualIntermediateFrequency.
You can set the desired values in the receiver System object for the following radio properties. However, due to quantization or range issues, the actual values can differ from your desired values. The actual values are stored in the properties that begin with Actual (see table).
|Parameter to Set||Actual Value|
The SDRADIFMCOMMSReceiver System object has an optional lost samples output port. When this port is active, it outputs a logical signal that indicates whether the System object is processing data in real time. If the System object is not keeping up with the hardware, the signal indicates the approximate number of lost samples.
This port is useful for determining real-time operation of the System objects. If your code is not running in real time, see Burst-Mode Buffering.
Direct conversion receivers, such as Analog Devices FMComms1 EBZ, often impose a DC bias on the in-phase and quadrature components of the signal. DC bias, if not dealt with, leads to degraded BER performance for QAM systems, and to a lesser extent, PSK systems. With the DC blocking filter implemented in the FPGA, the DC bias is reduced in the I/Q channels of a received complex signal, to better enable robust receiver processing, and allow you to focus on designing the baseband algorithm without worrying about DC bias that is introduced by the analog front end.
The DC blocking filter is on by default. To bypass this filter, set the BypassDCBlockingFilter property to 1, or true.
so = comm.SDRADIFMCOMMSReceiver
so = System: comm.SDRADIFMCOMMSReceiver Properties: IPAddress: '192.168.2.2' CenterFrequencySource: 'Property' CenterFrequency: 2400000000 ActualCenterFrequency: NaN IntermediateFrequencySource: 'Property' IntermediateFrequency: 0 ActualIntermediateFrequency: NaN GainSource: 'Property' Gain: 4.5 ActualGain: NaN ADCRate: 98000000 ActualADCRate: NaN DecimationFactor: 512 ActualDecimationFactor: NaN EnableBurstMode: false BypassUserLogic: false BypassDCBlockingFilter: false LostSamplesOutputPort: true OutputDataType: 'int16' FrameLength: 3660
so = System: comm.SDRADIFMCOMMSReceiver Properties: IPAddress: '192.168.2.2' CenterFrequencySource: 'Property' CenterFrequency: 2400000000 ActualCenterFrequency: NaN IntermediateFrequencySource: 'Property' IntermediateFrequency: 0 ActualIntermediateFrequency: NaN GainSource: 'Property' Gain: 4.5 ActualGain: NaN ADCRate: 98000000 ActualADCRate: NaN DecimationFactor: 512 ActualDecimationFactor: NaN EnableBurstMode: false BypassUserLogic: false BypassDCBlockingFilter: true LostSamplesOutputPort: true OutputDataType: 'int16' FrameLength: 3660
Configure an SDR board at the default IP address to receive at 2.5 GHz with an ADC rate of 100 MHz and a baseband rate of 1 MHz. Save the data using a signal logger System object.
hSDR = comm.SDRADIFMCOMMSReceiver( ... 'CenterFrequency', 2.5e9, ... 'ADCRate', 100e6, ... 'DecimationFactor', 100); hLogger = dsp.SignalLogger; for counter = 1:20 [data, dataLength] = step(hSDR); if (dataLength) step(hLogger, data); end end