Transmit data to Analog Devices FMCOMMS board
The SDRADIFMCOMMSTransmitter System object™ transmits data to a Xilinx® FPGA-based radio, allowing simulation and development for various software-defined radio applications. The SDRADIFMCOMMSTransmitter object enables communication with a FPGA board on the same Ethernet subnetwork.
The SDRADIFMCOMMSTransmitter System object is a signal sink that transmits data to an FPGA board.
The diagram shows how MATLAB®, the SDRADIFMCOMMSReceiver System object, and Xilinx FPGA hardware interface.
|Port||Supported Data Types|
The input port supports the following complex and real data types:
H=comm.SDRADIFMCOMMSTransmitter creates an SDR transmitter System object, H, that transmits data to an FPGA development motherboard with an Analog Devices FMCOMMS daughterboard installed. The System object enables communication with an SDR board on the same gigabit Ethernet subnetwork as the host.
H=comm.SDRADIFMCOMMSTransmitter(Name,Value) creates an SDR transmitter object, H, with the specified property Name set to the specified Value. You can specify additional name-value pair arguments in any order as (Name1,Value1,...,NameN,ValueN).
An SDRADIFMCOMMSTransmitter System object connects to a device when you call the step method, and stays connected until you call the release method.
IP address of the radio
Specify the logical network location of the radio as a string. The default is 192.168.0.2 for Epiq Solution radios and 192.168.2.2 for ADI radios.
Source of RF center frequency
Specify the source of the center frequency as Property or Input port. The default is Property. Set CenterFrequencySource to Input port to specify the center frequency value using an input to the step method. Set CenterFrequencySource to Property to specify the center frequency value using the CenterFrequency property.
RF center frequency in Hz
Specify the desired center frequency as a double-precision, nonnegative, finite scalar. This property applies when you set CenterFrequencySource to Property.
The default is 2.4 GHz. The valid range of values for this property is 400 MHz to 4 GHz.
Actual RF center frequency in Hz
Reports the actual center frequency of the daughterboard. Desired and actual center frequency can differ slightly due to quantization. The value is NaN when the actual value is unknown. Use synchronize to update the actual value. This property is read only.
Desired DAC sampling rate in Hz
Specify the desired codec rate as a double-precision nonnegative scalar. The default is 98 MHz. The valid range of this property is 39–100 MHz. This property applies when you set DACRateSource to Property.
Actual DAC sampling rate in Hz
Reports the actual sampling rate of the RF signal. Desired and actual sampling rate can differ slightly due to quantization. The value is NaN when the actual value is unknown. Use synchronize to update the actual value. This property is read only.
Desired interpolation factor
Specify the desired interpolation factor as a double-precision, nonnegative scalar. The default is 512. The baseband rate is DACRate / InterpolationFactor. See Interpolation Factors.
Actual interpolation factor
Reports the actual interpolation factor of the daughterboard. Desired and actual interpolation factor can differ slightly due to quantization. The value is NaN when the actual value is unknown. Use the method synchronize to update the actual value. This property is read only.
Output flag to indicate dropped samples
Set this property to true so that the step method outputs the number of lost samples during host-hardware data transfers.
The default value for LostSamplesOutputPort is false, which means that the port is not enabled and no information about dropped packets is displayed.
This port is useful for determining real-time operation of the System object. If your design is not running in real time, increase the decimation factor to approach or achieve real-time performance.
Ensure a set of frames without overrun or underrun
When set to true, this property produces a set of contiguous frames without an overrun or underrun to the radio. This setting can help simulate models that cannot run in real time. When you enable this property, specify the desired amount of contiguous data using the NumFramesInBurst property. The default value is false.
Number of frames in contiguous burst
This property is valid when EnableBurstMode property is set to true. The default number of frames in a burst is 20.
Bypass user logic from target workflow
When you enable this property, the FPGA data path bypasses the algorithm generated and programmed during the SDR workflow. This bypass can help with debugging system bringup. The default value is false, or not enabled.
|disconnect||Allow other host software to communicate with SDR board|
|info||Obtain SDR board information|
|isLocked||Locked status (logical)|
|release||Allow property value and input characteristics changes|
|step||Transmit data to SDR board|
|synchronize||Configure SDR board|
Verify that your SDRADIFMCOMMSTransmitter System object is connected to FPGA hardware by using the info method.
Construct an SDRADIFMCOMMSTransmitter System object.
h = comm.SDRADICOMMSTransmitter
Use the info method:
S = info(h)
The function returns the hardware information for object h in structure S .
The FPGA image includes an interpolating filter chain that is controlled by the Interpolation Factor parameter. The filter chain consists of two halfband filters followed by one CIC filter as shown in the diagram below. The first halfband filter has a sharper transition band and more filter weights than the second one. For this reason the first halfband is called Halfband Heavyweight (HBH) and the second is called Halfband Lightweight (HBL).
The filter chain supports interpolation factors from the following set of values:
[5:128, 130:2:256, 260:4:512]
Any integer from 5 to 128
A multiple of 2 from 130 to 256
A multiple of 4 from 260 to 512
Note: If the desired interpolation factor is not supported then it will be quantized to a supported value from the above set. Furthermore this may result in a suboptimal hardware configuration and is therefore not recommended. See the table below for examples.
Each halfband filter interpolates by a factor of 2 and may be bypassed if necessary. The CIC filter has a variable interpolation factor (CIC rate) of between 2 and 128 and may also be bypassed. The filters are enabled or bypassed according to the following rules:
If the desired interpolation factor is divisible by 4, then both HBH and HBL are enabled.
If the desired interpolation factor is divisible by 2 and not by 4, then HBH is enabled and HBL is bypassed.
If the desired interpolation factor is not divisible by 2, then HBH and HBL are both bypassed.
The remaining interpolation factor is made up by the CIC filter. If the remaining factor is 1, then the CIC is bypassed.
|Desired Interpolation Factor||HBH||HBL||CIC||Actual Interpolation Factor||Recommended|
The Support Package for Xilinx FPGA-Based Radio software incorporates the logic to determine these settings automatically from the desired interpolation factor block mask parameter.
When you set property values for center frequency and gain, the System object initially performs some rudimentary checks that the values are scalar and real. If your values pass those checks, you can still provide values that are out of range for the FPGA-based radio. In that case, the hardware makes a best effort to set the requested value, and reports the actual value in the Device value column of the block mask.
The SDRADIFMCOMMSTransmitter System object has an optional lost samples output port. When this port is active, it outputs a logical signal that indicates whether the System object is processing data in real time. If the System object is not keeping up with the hardware, the signal indicates the approximate number of lost samples.
This port is useful for determining real time operation of the System objects. If your code is not running in real time, see Apply Burst-Mode Buffering.
Configure an SDR board with an IP address of 192.168.0.2 to transmit at 2.4 GHz with a codec rate of 100 MHz and a baseband rate of 1 MHz. Use a DPSK modulator as the data source.
hSDR = comm.SDRADIFMCOMMSTransmitter( ... 'IPAddress', '192.168.0.2', ... 'CenterFrequency', 2.4e9, ... 'DACRate', 100e6, ... 'InterpolationFactor', 100); hMod = comm.DPSKModulator('BitInput',true); for counter = 1:20 data = randi([0 1], 30, 1); modSignal = step(hMod, data); step(hSDR, modSignal); end