Receive data from Epiq Solution's Bitshark RF board
The SDREpiqBitsharkReceiver System object™ receives data from a Xilinx® FPGA-based radio, allowing simulation and development for various software-defined radio applications. The SDREpiqBitsharkReceiver object enables communication with an FPGA board on the same Ethernet subnetwork.
The SDREpiqBitsharkReceiver System object is a signal source that receives data from an FPGA board and outputs a column vector signal of fixed length. The first call to this object can contain transient values, which results in packets containing undefined data.
The diagram shows how MATLAB®, the SDREpiqBitsharkReceiver System object, and Xilinx FPGA hardware interface.
When this System object is called, the host might not have received any data from the Xilinx FPGA hardware. The data length, Len, indicates when valid data is present. When the data length port contains a zero value, there is no data. You can use the data length, if Len > 0, to qualify the execution of part of the code.
|Port||Supported Data Types|
The output port supports these complex data types only:
H = comm.SDREpiqBitsharkReceiver creates an SDR receiver System object, H, that receives data from an FPGA development motherboard with an Epiq Solution's Bitshark™ FMC-1Rx daughterboard installed. The System object enables communication with an SDR board on the same gigabit Ethernet subnetwork as the host.
H = comm.SDREpiqBitsharkReceiver(Name,Value) creates an SDR receiver System object, H, with the specified property Name set to the specified Value. You can specify additional name-value pair arguments in any order as (Name1,Value1,...,NameN,ValueN).
An SDREpiqBitsharkReceiver System object connects to a device when you call the step method and stays connected until you call the release method.
IP address of the SDR device
Specify the logical network location of the SDR device as a string. The default is Select device. This property lists all discovered SDR devices on the same subnet as the host computer. To use tab completion to query valid IPAddress assignments for your computer, type H.IPAddress = ' and press Tab.
Source of the center frequency
Specify the source of the center frequency as Property or Input port. The default is Property. Set RFFrequencySource to Input port to specify the center frequency value using an input to the step method. Set CenterFrequencySource to Property to specify the center frequency value using the RFFrequency property.
Desired center frequency in hertz
Specify the desired center frequency as a double-precision, nonnegative, finite scalar. This property applies when you set the RFFrequencySource to Property.
The default is 2.4 GHz. The valid range of values for this property is 300 MHz to 4 GHz.
Actual center frequency in hertz
Report the actual center frequency of the daughterboard. Desired and actual center frequency can differ slightly due to quantization. This property is read only.
Source of bandwidth for IF filter
Desired IF bandwidth in Hz
Actual IF bandwidth in Hz
Source of the gain
Specify the source of the gain as one of Property or Input port. The default is Property. Set GainSource to Input port to specify the gain value using an input to the step method. Set GainSource to Property to specify the gain value using the Gain property.
Desired RF front-end gain in dB
Actual RF front-end gain in dB
Report the actual gain of the daughterboard. Desired and actual gain can differ slightly due to quantization. This property is read only.
Desired ADC sample rate. The default value is 100 MHz. The valid range for this board is 5–105 MHz.
Actual ADC sample rate in samples per second
Desired decimation factor
Specify the desired decimation factor as a double-precision nonnegative scalar. The default is 512. The baseband rate is ADCRate/DecimationFactor. See Decimation Factors.
Actual decimation factor
Reports the actual decimation factor of the daughterboard. Desired and actual decimation factor can differ slightly due to quantization. The value is NaN when the actual value is unknown. Use the synchronize method to update the actual value. This property is read only.
Output flag to indicate dropped samples
Set this property to true to specify for the step method to output the number of lost samples during host/hardware data transfers. Non zero values indicate that the host cannnot keep up with the radio data rates. The default is false.
This port is useful for determining the real-time operation of the System object. If your model is not running in real time, increase the decimation factor to approach or achieve real-time performance.
Data type of output
Specify the data type of the output signal as double, single, or int16. The default is int16, with a range of [-32768, 32767]. This block supports the following complex output data types:
When you set OutputDataType to double-precision floating point or single-precision floating point, the range is [-1, 1].
Specify the frame length of the output signal that the object generates as a positive, scalar integer. The default value is 362. This value optimally utilizes the underlying Ethernet packets, which have a size of 1500 8-bit bytes.
Ensure a set of frames without overrun
When set to true, this property produces a set of contiguous frames without an overrun or underrun to the radio. This setting can help simulate models that cannot run in real time. When you enable this property, specify the desired amount of contiguous data using the NumFramesInBurst property. The default value is false.
Number of frames in contiguous burst
This property is valid when EnableBurstMode property is set to true. The default number of frames in a burst is 100.
Bypass user logic from target workflow
When you enable this property, the FPGA data path bypasses the algorithm generated and programmed during the SDR workflow. This bypass can help with debugging system bringup. The default value is false, or not enabled.
|disconnect||Allow other host software to communicate with SDR board|
|info||Obtain SDR board informaion|
|isLocked||Locked status (logical)|
|release||Allow property value and input characteristics changes|
|step||Receive data from SDR board|
|synchronize||Configure SDR board|
Verify that your SDREpiqBitsharkReceiver System object is connected to FPGA hardware by using the info method.
Construct an SDREpiqBitsharkReceiver System object.
h = comm.SDREpiqBitsharkReceiver
Use the info method:
S = info(h)
The function returns the hardware information for object h in structure S.
The System object determines the radio frequency sample times using the ADC clock rate, decimation factor, and frame size, according to the following formula: Sample time = 1/(ADCRate/DecimationFactor). You can choose to use decimation to reduce your bandwidth. See Decimation Factors.
The FPGA image includes a decimation filter chain that is controlled by the Decimation Factor parameter. The filter chain consists of a CIC filter followed by two halfband filters as shown in the diagram below. The first halfband filter has a wider transition band and less filter weights than the second one. For this reason the first halfband is called Halfband Lightweight (HBL) and the second is called Halfband Heavyweight (HBH).
The filter chain supports decimation factors from the following set of values:
Any integer from 4 to 128
A multiple of 2 from 130 to 256
A multiple of 4 from 260 to 512
Note: If the desired decimation factor is not supported then it will be quantized to a supported value from the above set. Furthermore this may result in a suboptimal hardware configuration and is therefore not recommended. See the table below for examples.
The CIC filter has a variable decimation factor (CIC rate) of between 2 and 128 and may be bypassed if necessary. Each halfband filter decimates by a factor of 2 and may be also be bypassed. The filters are enabled or bypassed according to the following rules:
If the desired decimation factor is divisible by 4, then both HBL and HBH are enabled.
If the desired decimation factor is divisible by 2 and not by 4, then HBL is bypassed and HBH is enabled.
If the desired decimation factor is not divisible by 2, then HBL and HBH are both bypassed.
The remaining decimation factor is made up by the CIC filter. If the remaining factor is 1 then the CIC is bypassed.
The following table demonstrates some examples of how the filter chain is configured to implement the desired decimation factor:
|Desired Decimation Factor||CIC||HBL||HBH||Actual Decimation Factor||Recommended|
The Support Package for Xilinx FPGA-Based Radio software incorporates the logic to determine these settings automatically from the desired decimation factor block mask parameter.
You can set your desired values in the receiver System object for center frequency, gain, and bandwidth. However, due to quantization or range issues, the actual values can differ from your desired values. The actual values are stored in the properties that begin with Actual.
|Parameter to Set||Actual Value|
The SDREpiqBitsharkReceiver System object has an optional lost samples output port. When this port is active, it outputs a logical signal that indicates whether the System object is processing data in real time. If the System object is not keeping up with the hardware, the signal indicates the approximate number of lost samples.
This port is useful for determining real-time operation of System objects. If your code is not running in real time, see Apply Burst-Mode Buffering.
Configure an SDR board with an IP address of 192.168.0.2 to receive at 2.5 GHz with a codec rate of 100 MHz and a baseband rate of 1 MHz. Save the data using a signal logger System object.
hSDR = comm.SDREpiqBitsharkReceiver( ... 'IPAddress', '192.168.0.2', ... 'CenterFrequency', 2.5e9, ... 'ADCRate', 100e6, ... 'DecimationFactor', 100); hLogger = dsp.SignalSink; for counter = 1:20 [data, dataLength] = step(hSDR); if (dataLength) step(hLogger, data); end end