Receive data from Epiq Solution's Bitshark board
The Epiq Bitshark Receiver block supports communication between Simulink® and a Xilinx® FPGA-based radio device, allowing simulation and development for various software-defined radio applications. The Epiq Bitshark Receiver block enables communication with a Xilinx FPGA board on the same Ethernet subnetwork.
The Epiq Bitshark Receiver block is a signal sink that receives data from a Xilinx FPGA board and outputs a column vector signal of fixed length. The first call to this block may contain transient values which result in packets containing undefined data.
The following block diagram illustrates the interaction between Simulink, the Epiq Bitshark Receiver block, and the Xilinx FPGA device.
When this block is called, it is possible that the host may not have received any data from the Xilinx FPGA hardware. The data length port, DataLength, indicates when valid data is present. When the data length port contains a zero value, there is no data. You can use the data length with an enabled subsystem to qualify the execution of part of the model.
If your computer is not connected to any Xilinx FPGA hardware, you can still use this block to develop a model that propagates sample time and data type information. To propagate this information, select Edit > Update diagram; alternatively, you can press Ctrl + D.
To open the SDR Block library, enter the following at the MATLAB® prompt:
The following diagram illustrates the data path for radio signal reception (when the decimation filter, IF tuner, and DC blocking filter are all in use in the block):
|Port||Supported Data Types|
The output port supports these complex data types only:
When you select a double or single data type, the complex values are scaled to the range of [-1,1]. When you select int16, the complex values are the raw 16-bit I and Q samples from the board.
Specify the logical network location of the radio as a string. The default IP address is 192.168.0.2 for Epiq Solution radios.
Configure the SDR board and read back the actual hardware values.
Center frequency in Hz
Specify the desired center frequency as a double-precision, nonnegative, finite scalar. The default is 2.4GHz. The valid range of values for this parameter is 300MHz to 4GHz.
The intermediate frequency (IF) tuner allows you to account for the error in tuning between target center frequency and actual center frequency and avoid unwanted interference by shifting it out of the pass band of interest. Choose either Dialog or Input port as the source of the center frequency value. If you choose Dialog, specify the desired center frequency as a double-precision, finite scalar. The default value is 0 Hz. The valid range of values for this parameter is to , where is the analog-digital converter (ADC) rate.
Desired IF bandwidth in Hz.
Desired RF front-end gain in dB.
Desired ADC sampling rate. The default is 100MHz. The valid range for this board is 5–105MHz.
Desired decimation factor as a double precision nonnegative scalar. The default is 512. The baseband rate is ADC sampling rate / Decimation factor. See Decimation Factors.
Enable lost samples port
Select this option so that the block outputs a value to indicate if one or more packets is dropped during host reception of FPGA hardware data.
Zero indicates no data loss
A positive number indicates that overruns or underruns occurred
This port is a useful diagnostic tool to determine real time operation of the receiver block. If your model is not running in real time, you can increase the decimation factor to approach or achieve real-time performance.
Select the data type of the output signal. The default is int16, with a range of [-32768, 32767]. This block supports the following complex output data types:
Double-precision floating point
Single-precision floating point
16-bit signed integers
When you set Output data type to either Double-precision floating point or Single-precision floating point, the range is [-1, 1].
Specifies the sample time for a single radio sample. For the Simulink sample time to correspond to real time, use the following formula: Sample time = 1/(ADC sampling rate/Decimation factor). The default setting for this parameter is 1.
Specify the frame length of the output signal that the block generates as a positive, scalar integer. Using values less than 366 is not recommended as it may yield very poor performance. The default value is 3660.
Ensure a set of frames without overruns.
When selected, this option produces a set of contiguous frames without an overrun frame to the radio. This setting can help simulate models that cannot run in real time. When enabled, specify the desired amount of contiguous data using the Number of frames in burst option. The default value is not selected.
Number of frames in contiguous burst
This parameter is valid and visible only when the Enable burst mode parameter is selected. The default number of frames in a burst is 20.
Bypass the DC bias removal filter. When you select this parameter, the DC blocking filter to automatically reduce a DC bias is bypassed. Enable this when the filter is also blocking some signal and you need to use a different DC bias compensation scheme. By default, this option is not selected, which means to include the automatic DC blocking filter.
When you select this option, the FPGA data path bypasses the custom design under test (DUT) logic that is generated and programmed during the SDR Targeting workflow. This bypass helps with debugging system bringup. By default, this option is selected.
Communicate with the attached radio to obtain basic hardware information. The information is displayed in the Hardware Information pane.
You can verify that your Epiq Bitshark Receiver block is connected to FPGA hardware with the Info button on the block.
Open the block mask.
Click the Info button.
If the block is not connected, the panel will show the following message:
No attached SDR hardware or unable to retrieve hardware information.
Support package for Xilinx FPGA-Based Radio determines the radio frequency sample times using the ADC clock rate, decimation factor, and frame size, according to the following formula: Sample time = 1/(ADC sampling rate/Decimation factor).
You can choose to use decimation to reduce your bandwidth. See the description for Decimation factor.
The FPGA image includes a decimation filter chain that is controlled by the Decimation Factor parameter. The filter chain consists of a CIC filter followed by two halfband filters as shown in the diagram below. The first halfband filter has a wider transition band and less filter weights than the second one. For this reason the first halfband is called Halfband Lightweight (HBL) and the second is called Halfband Heavyweight (HBH).
The filter chain supports decimation factors from the following set of values:
Any integer from 4 to 128
A multiple of 2 from 130 to 256
A multiple of 4 from 260 to 512
Note: If the desired decimation factor is not supported then it will be quantized to a supported value from the above set. Furthermore this may result in a suboptimal hardware configuration and is therefore not recommended. See the table below for examples.
The CIC filter has a variable decimation factor (CIC rate) of between 2 and 128 and may be bypassed if necessary. Each halfband filter decimates by a factor of 2 and may be also be bypassed. The filters are enabled or bypassed according to the following rules:
If the desired decimation factor is divisible by 4, then both HBL and HBH are enabled.
If the desired decimation factor is divisible by 2 and not by 4, then HBL is bypassed and HBH is enabled.
If the desired decimation factor is not divisible by 2, then HBL and HBH are both bypassed.
The remaining decimation factor is made up by the CIC filter. If the remaining factor is 1 then the CIC is bypassed.
The following table demonstrates some examples of how the filter chain is configured to implement the desired decimation factor:
|Desired Decimation Factor||CIC||HBL||HBH||Actual Decimation Factor||Recommended|
The Support Package for Xilinx FPGA-Based Radio software incorporates the logic to determine these settings automatically from the desired decimation factor block mask parameter.
Intermediate frequency (IF) tuning supports second stage tuning for both the transmit and receive data paths. The tuner is configurable at run-time (tunable), provides finer resolution when compared to the primary tuner on an RF card, and allows you to remove unwanted interference from the pass band of interest.
IF Tuning on Receive Data Path
To enable an intermediate frequency tuner, set the Intermediate Frequency parameter in the block mask for the receiver block.
Receiver Block IF Tuning
When you set block values for center frequency, intermediate frequency, IF bandwitdth, gain, ADC and decimation, the block initially performs some rudimentary checks that the values are scalar and real. If your values pass those checks, you can still provide values that are out of range for the FPGA-based radio. In that case, the hardware will make a best effort to set the requested value, and will report the actual value in the Device value column of the block mask.
The Epiq Bitshark Receiver block has an optional lost samples output port. When this port is active, it outputs a logical signal that indicates whether the block is processing data in real time. If the block is not keeping up with the hardware, the signal goes high.
This port is a useful diagnostic tool for determining real time operation of the blocks. If your model is not running in real time, see Xilinx FPGA-Based Radio Processing Errors and Fixes.
Direct conversion receivers, such as Epic's Bitshark™ receiver, often impose a DC bias on the in-phase and quadrature components of the signal. DC bias, if not dealt with, leads to degraded BER performance for QAM systems, and to a lesser extent, PSK systems. With the DC blocking filter implemented in the FPGA, the DC bias is reduced in the I/Q channels of a received complex signal, to better enable robust receiver processing, and allow you to focus on designing the baseband algorithm without worrying about DC bias that is introduced by the analog front end.
The DC blocking filter is on by default. To bypass this filter, Select Bypass DC blocking filter in the Datapath Configuration section of the receiver block mask: