Documentation

Code Generation

Simulation acceleration, code generation, optimization for ARM® Cortex®-M Processors and ARM Cortex-A Processors

Generate C or C++ source code, or a MEX function from DSP System Toolbox™ signal processing algorithms using MATLAB® Coder™ and Simulink® Coder. To learn how to generate C code, see Understanding C Code Generation. In addition, you can generate code optimized for ARM Cortex-M Processors and ARM Cortex-A Processors using Embedded Coder®. For more information, see ARM Cortex-M and ARM Cortex-A Optimization. You can also tune your algorithm parameters directly from MATLAB or Simulink in real time via the UI while your generated C code executes on the desktop.

With the dspunfold function, you can generate a multithreaded MEX file, which leverages the multicore CPU architecture of the host computer. To use this function, you must have a MATLAB Coder license.

To deploy a filter onto FPGAs and ASICs, generate synthesizable and portable VHDL® and Verilog® code from the filter using Filter Design HDL Coder™. You can also create VHDL and Verilog test benches for quickly simulating, testing, and verifying the generated code. DSP System Toolbox, when used with HDL Coder™ in Simulink, provides synthesizable and readable VHDL and Verilog code generation for your system design. This support includes algorithms optimized for resource and performance, such as the FFT HDL Optimized, IFFT HDL Optimized, and NCO HDL Optimized filters. For an example that shows how to generate HDL code, see Generate HDL Code for Programmable FIR Filter.

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