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Generate HDL Code for Multichannel FIR Filter

This example demonstrates how to generate HDL code for a discrete FIR filter with multiple input data streams.

In many DSP applications, multiple data streams are filtered by the same filter. The straightforward solution is to implement a separate filter for each channel. If possible, a more area-efficient structure can be applied by sharing one filter implementation among multiple channels. The resulting hardware requires a faster clock with respect to the sample rate for a single channel filter.

Prerequisites

You require an HDL Coder™ license to run this example.

Model Multichannel FIR Filter

Enter the following commands to open the example model:

modelname = 'dspmultichannelhdl';
open_system(modelname);

Consider a two-channel FIR filter. The input data vector includes two streams of sinusoidal signal with different frequencies. The input data streams are processed by a lowpass filter, whose coefficients are specified by the Model Properties InitFcn Callback function.

Enter the following commands to specify the fully parallel architecture implementation to the Discrete FIR Filter block:

systemname = [modelname '/Multichannel FIR Filter'];
blockname = [systemname '/Discrete FIR Filter'];
set_param(blockname,'FilterStructure','Direct form symmetric');
hdlset_param(blockname, 'Architecture', 'Fully Parallel');

Enter the following commands to allow for resource sharing among multiple channels:

hdlset_param(blockname, 'ChannelSharing', 'On');

You can also specify these settings on the HDL Block Properties menu.

Simulation Results

Enter the following command to run the example model:

sim(modelname);

Enter the following command to open the scope:

open_system([modelname '/Scope']);

Compare the two output data streams.

Enter the following command to close the scope:

close_system([modelname '/Scope']);

Generate HDL Code and Test Bench

Get a unique temporary directory name for the generated files:

workingdir = tempname;

You can enter the following command to validate the parameter settings of the Multichannel FIR Filter block:

checkhdl(systemname,'TargetDirectory',workingdir);

Enter the following command to generate HDL code:

makehdl(systemname,'TargetDirectory',workingdir);
### Generating HDL for 'dspmultichannelhdl/Multichannel FIR Filter'.
### Starting HDL check.
### The code generation and optimization options you have chosen have introduced additional pipeline delays.
The delay balancing feature has automatically inserted matching delays for compensation.
### The DUT requires an initial pipeline setup latency. Each output port experiences these additional delays.
### Output port 0: 2 cycles.
### Begin VHDL Code Generation for 'dspmultichannelhdl'.
### MESSAGE: The design requires 2 times faster clock with respect to the base rate = 0.0005.
### Working on Multichannel FIR Filter_tc as /tmp/BR2014bd_145981_71764/tpd14423bf_9170_4e29_9d61_c4014b39b420/dspmultichannelhdl/Multichannel_FIR_Filter_tc.vhd.
### Working on dspmultichannelhdl/Multichannel FIR Filter as /tmp/BR2014bd_145981_71764/tpd14423bf_9170_4e29_9d61_c4014b39b420/dspmultichannelhdl/Multichannel_FIR_Filter.vhd.
### Working on dspmultichannelhdl/Multichannel FIR Filter/Discrete FIR Filter as /tmp/BR2014bd_145981_71764/tpd14423bf_9170_4e29_9d61_c4014b39b420/dspmultichannelhdl/Discrete_FIR_Filter.vhd.
### Starting VHDL code generation process for filter: Discrete_FIR_Filter
### Generating: <a href="matlab:edit('/tmp/BR2014bd_145981_71764/tpd14423bf_9170_4e29_9d61_c4014b39b420/dspmultichannelhdl/Discrete_FIR_Filter.vhd')">/tmp/BR2014bd_145981_71764/tpd14423bf_9170_4e29_9d61_c4014b39b420/dspmultichannelhdl/Discrete_FIR_Filter.vhd</a>
### Starting generation of Discrete_FIR_Filter VHDL entity
### Starting generation of Discrete_FIR_Filter VHDL architecture
### Successful completion of VHDL code generation process for filter: Discrete_FIR_Filter
### HDL latency of filter is 1 output samples
### Additional HDL synchronization latency of 1 sample added
### Generating package file /tmp/BR2014bd_145981_71764/tpd14423bf_9170_4e29_9d61_c4014b39b420/dspmultichannelhdl/Multichannel_FIR_Filter_pkg.vhd.
### Creating HDL Code Generation Check Report file:////tmp/BR2014bd_145981_71764/tpd14423bf_9170_4e29_9d61_c4014b39b420/dspmultichannelhdl/Multichannel_FIR_Filter_report.html
### HDL check for 'dspmultichannelhdl' complete with 0 errors, 0 warnings, and 0 messages.
### HDL code generation complete.

Enter the following command to generate the test bench:

makehdltb(systemname,'TargetDirectory',workingdir);
### Begin TestBench generation.
### Generating HDL TestBench for 'dspmultichannelhdl/Multichannel FIR Filter'.
### Begin simulation of the model 'gm_dspmultichannelhdl'...
### Collecting data...
### Generating test bench: /tmp/BR2014bd_145981_71764/tpd14423bf_9170_4e29_9d61_c4014b39b420/dspmultichannelhdl/Multichannel_FIR_Filter_tb.vhd
### Creating stimulus vectors ...
### HDL TestBench generation complete.
 

Compare Resource Utilization

You can enter the following command to show resource report with channel sharing:

makehdl(systemname,'TargetDirectory',workingdir, 'resource', 'on');

You can enter the following command to show resource report without channel sharing:

hdlset_param(blockname, 'ChannelSharing', 'Off'); makehdl(systemname,'TargetDirectory',workingdir, 'resource', 'on');

You can see the different resource utilization by comparing the two reports:

This ends the Generate HDL Code for Multichannel FIR Filter example.

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