Compute magnitude and/or phase angle of complex signal—optimized for HDL code generation using the CORDIC algorithm
Math Operations
dspmathops
The Complex to MagnitudeAngle HDL Optimized block computes the magnitude and/or phase angle of a complex signal. It provides hardwarefriendly control signals. The block uses a pipelined Coordinate Rotation Digital Computer (CORDIC) algorithm to achieve an efficient HDL implementation.
Port  Direction  Description  Data Type 

dataIn  Input  Complex scalar input data. 

validIn  Input  Indicates that the input data is valid. When validIn is
high, the block captures the dataIn value.  boolean 
magnitude  Output  Scalar output data.  Same as dataIn 
angle  Output  Scalar output data. Optional.  Same as dataIn 
validOut  Output  Indicates that the output data is valid. When the magnitude or angle output
is ready, the block sets validOut high .  boolean 
Specifies the source of Number of iterations for
the CORDIC algorithm. Select Auto
to set
the number of iterations to the input word length − 1. If the
input is double
or single
, Auto
sets
the number of iterations to 16. Select Property
to
set the number of iterations from Number of iterations.
The default is Auto
.
Specifies the number of CORDIC iterations the block executes.
This parameter is visible only when Number of iterations
source is set to Property
.
The number of iterations must be less than or equal to the input data
word length − 1.
The latency of the block depends on the number of iterations performed. See Latency.
Specifies which output ports are active. You can select Magnitude
, Angle
,
or Magnitude and angle
. The default is Magnitude
and angle
.
Specifies the format of the angle
output.
You can select Normalized
or Radians
.
Select Normalized
to return output in a
fixedpoint format that normalizes the angles in the range [–1,1].
For more information see Normalized Angle Format. Select Radians
to
return output as a fixedpoint value between π and −π.
The default format is Normalized
.
Scales output by the inverse of the CORDIC gain factor. The default value is selected.
If you turn off output scaling, and apply the CORDIC gain elsewhere in your design, you must exclude the π/4 term. The quadrant mapping algorithm replaces the first CORDIC iteration by mapping inputs onto the angle range [0,π/4]. Therefore, the initial rotation does not contribute a gain term.
If the input is 0+0i, the output angle is undefined. The block does not implement correction logic to force the output to 0. You can ignore this output angle.
The CORDIC algorithm is a hardwarefriendly method for performing trigonometric functions. It is an iterative algorithm that approximates the solution by converging toward the ideal point. The block uses CORDIC vectoring mode to iteratively rotate the input onto the real axis.
The Givens method for rotating a complex number x+iy by an angle θ is as follows. The direction of rotation, d, is +1 for counterclockwise and −1 for clockwise.
$$\begin{array}{l}{x}_{r}=x\mathrm{cos}\theta dy\mathrm{sin}\theta \\ {y}_{r}=y\mathrm{cos}\theta \text{}+dx\mathrm{sin}\theta \end{array}$$
$$\begin{array}{l}{x}_{r}=\mathrm{cos}\theta \left(xdy\mathrm{tan}\theta \right)\\ {y}_{r}=\mathrm{cos}\theta \left(y+dx\mathrm{tan}\theta \right)\end{array}$$
To rotate the vector onto the real axis, choose a series of rotations of θ_{n} so that $$\mathrm{tan}{\theta}_{n}={2}^{n}$$. Remove the cosθ term so each iterative rotation uses only shift and add operations.
$$\begin{array}{l}R{x}_{n}={x}_{n1}{d}_{n}{y}_{n1}{2}^{n}\\ R{y}_{n}={y}_{n1}+{d}_{n}{x}_{n1}{2}^{n}\end{array}$$
$$\begin{array}{l}{x}_{r}=\left(\mathrm{cos}{\theta}_{0}\mathrm{cos}{\theta}_{1}\mathrm{...}\mathrm{cos}{\theta}_{n}\right)R{x}_{N}\\ z={\displaystyle \sum _{0}^{N}{d}_{n}{\theta}_{n}}\end{array}$$
The convergence region for the standard CORDIC rotation is ≈±99.7°. To work around this limitation, before doing any rotation, the block maps the input into the [0,π/4] range using the following algorithm.
if abs(x) > abs(y) input_mapped = [abs(x), abs(y)]; else input_mapped = [abs(y), abs(x)]; end
Quadrant mapping saves hardware resources and reduces latency by reducing the number of CORDIC pipeline stages by one. The CORDIC gain factor, Kn, therefore does not include the n=0, or cos(π/4) term.
$${K}_{n}=cos{\theta}_{1}\mathrm{...}\mathrm{cos}{\theta}_{n}=\text{cos}(26.565)\cdot \text{cos}(14.036)\cdot \text{cos}(7.125)\cdot \text{cos}(3.576)$$
After the CORDIC iterations are complete, the block corrects the angle back to its original location. First it adjusts the angle to the correct side of π/4.
if abs(x) > abs(y) angle_unmapped = CORDIC_out; else angle_unmapped = (pi/2)  CORDIC_out; end
if (x < 0) if (y < 0) output_angle =  pi + angle_unmapped; else output_angle = pi  angle_unmapped; else if (y<0) output_angle = angle_unmapped;
The block generates a pipelined HDL architecture to maximize throughput. Each CORDIC iteration is done in one pipeline stage. The gain multiplier, if enabled, is implemented with Canonical Signed Digit (CSD) logic.
Input Word Length  Output Magnitude Word Length 

fixdt(0,WL,FL)  fixdt(0,WL+2,FL) 
fixdt(1,WL,FL)  fixdt(1,WL+1,FL) 
Input Word Length  Output Angle Word Length  

fixdt([ ],WL,FL)  Radians  fixdt(1,WL+3,WL) 
Normalized  fixdt(1,WL+3,WL+2) 
The CORDIC logic at each pipeline stage implements one iteration. For each pipeline stage, the shift and angle rotation are constants.
When you set Output format to Magnitude
,
the block does not generate HDL code for the angle accumulation and
quadrant correction logic.
This format normalizes the fixedpoint radian angle values around the unit circle. This is a more efficient use of bits than a range of [0,2π] radians. Normalized angle format also enables wraparound at 0/2π without additional detect and correct logic.
For example, representing the angle with 3 bits results in the following normalized values.
Using the mapping described in Modified CORDIC Algorithm, the block normalizes the angles across [0,π/4] and maps them to the correct octant at the end of the calculation.
The validIn
signal qualifies the input data.
When the output data calculated from a valid input reaches the end
of the pipeline, the block asserts the validOut
signal.
The output is valid Number of iterations + 2 cycles after valid input.
When you set Number of iterations source
to Property
, the block shows the latency
immediately. When you set Number of iterations source
to Auto
, the block calculates the latency
based on the input port data type, and displays it when you update
the model.
When you set Number
of iterations source to Auto
,
the number of iterations is input word length − 1, and the
latency is input word length + 1. If the input is double
or single
type,
the number of iterations is 16, and the latency is 18.
This block supports HDL code generation using HDL Coder™. HDL Coder provides additional configuration options that affect HDL implementation and synthesized logic. For more information on implementations, properties, and restrictions for HDL code generation, see Complex to MagnitudeAngle HDL Optimized in the HDL Coder documentation.
Performance was measured for the default configuration, with output scaling disabled and
fixdt(1,16,12)
input. When the generated HDL code is synthesized into
a Xilinx^{®}
Virtex^{®}6 (XC6VLX240T1FFG1156) FPGA, the design achieves 260 MHz clock frequency. It
uses the following resources.
Resource  Number Used 

LUT  882 
FFS  792 
Xilinx LogiCORE^{®} DSP48  0 
Block RAM (16K)  0 
Performance of the synthesized HDL code varies depending on your target and synthesis options.
Complex to MagnitudeAngle  dsp.HDLComplexToMagnitudeAngle