Compute magnitude and/or phase angle of complex signal—optimized for HDL code generation using the CORDIC algorithm
The Complex to Magnitude-Angle HDL Optimized block computes the magnitude and/or phase angle of a complex signal. It provides hardware-friendly control signals. The block uses a pipelined Coordinate Rotation Digital Computer (CORDIC) algorithm to achieve an efficient HDL implementation.
|Input||Complex scalar input data.||
|Input||Indicates that the input data is valid. When |
|Output||Scalar output data.||Same as |
|Output||Scalar output data. Optional.||Same as |
|Output||Indicates that the output data is valid. When the |
Specifies the source of Number of iterations for
the CORDIC algorithm. Select
Auto to set
the number of iterations to the input word length − 1. If the
the number of iterations to 16. Select
set the number of iterations from Number of iterations.
The default is
Specifies the number of CORDIC iterations the block executes.
This parameter is visible only when Number of iterations
source is set to
The number of iterations must be less than or equal to the input data
word length − 1.
The latency of the block depends on the number of iterations performed. See Latency.
Specifies which output ports are active. You can select
Magnitude and angle. The default is
Specifies the format of the
You can select
Normalized to return output in a
fixed-point format that normalizes the angles in the range [–1,1].
For more information see Normalized Angle Format. Select
return output as a fixed-point value between π and −π.
The default format is
Scales output by the inverse of the CORDIC gain factor. The default value is selected.
If you turn off output scaling, and apply the CORDIC gain elsewhere in your design, you must exclude the π/4 term. The quadrant mapping algorithm replaces the first CORDIC iteration by mapping inputs onto the angle range [0,π/4]. Therefore, the initial rotation does not contribute a gain term.
If the input is 0+0i, the output angle is undefined. The block does not implement correction logic to force the output to 0. You can ignore this output angle.
The CORDIC algorithm is a hardware-friendly method for performing trigonometric functions. It is an iterative algorithm that approximates the solution by converging toward the ideal point. The block uses CORDIC vectoring mode to iteratively rotate the input onto the real axis.
The Givens method for rotating a complex number x+iy by an angle θ is as follows. The direction of rotation, d, is +1 for counterclockwise and −1 for clockwise.
To rotate the vector onto the real axis, choose a series of rotations of θn so that . Remove the cosθ term so each iterative rotation uses only shift and add operations.
The convergence region for the standard CORDIC rotation is ≈±99.7°. To work around this limitation, before doing any rotation, the block maps the input into the [0,π/4] range using the following algorithm.
if abs(x) > abs(y) input_mapped = [abs(x), abs(y)]; else input_mapped = [abs(y), abs(x)]; end
Quadrant mapping saves hardware resources and reduces latency by reducing the number of CORDIC pipeline stages by one. The CORDIC gain factor, Kn, therefore does not include the n=0, or cos(π/4) term.
After the CORDIC iterations are complete, the block corrects the angle back to its original location. First it adjusts the angle to the correct side of π/4.
if abs(x) > abs(y) angle_unmapped = CORDIC_out; else angle_unmapped = (pi/2) - CORDIC_out; end
if (x < 0) if (y < 0) output_angle = - pi + angle_unmapped; else output_angle = pi - angle_unmapped; else if (y<0) output_angle = -angle_unmapped;
The block generates a pipelined HDL architecture to maximize throughput. Each CORDIC iteration is done in one pipeline stage. The gain multiplier, if enabled, is implemented with Canonical Signed Digit (CSD) logic.
|Input Word Length||Output Magnitude Word Length|
|Input Word Length||Output Angle Word Length|
The CORDIC logic at each pipeline stage implements one iteration. For each pipeline stage, the shift and angle rotation are constants.
When you set Output format to
the block does not generate HDL code for the angle accumulation and
quadrant correction logic.
This format normalizes the fixed-point radian angle values around the unit circle. This is a more efficient use of bits than a range of [0,2π] radians. Normalized angle format also enables wraparound at 0/2π without additional detect and correct logic.
For example, representing the angle with 3 bits results in the following normalized values.
Using the mapping described in Modified CORDIC Algorithm, the block normalizes the angles across [0,π/4] and maps them to the correct octant at the end of the calculation.
validIn signal qualifies the input data.
When the output data calculated from a valid input reaches the end
of the pipeline, the block asserts the
The output is valid Number of iterations + 2 cycles after valid input.
When you set Number of iterations source
Property, the block shows the latency
immediately. When you set Number of iterations source
Auto, the block calculates the latency
based on the input port data type, and displays it when you update
When you set Number
of iterations source to
the number of iterations is input word length − 1, and the
latency is input word length + 1. If the input is
the number of iterations is 16, and the latency is 18.
This block supports HDL code generation using HDL Coder™. HDL Coder provides additional configuration options that affect HDL implementation and synthesized logic. For more information on implementations, properties, and restrictions for HDL code generation, see Complex to Magnitude-Angle HDL Optimized in the HDL Coder documentation.
Performance was measured for the default configuration, with output scaling disabled and
fixdt(1,16,12) input. When the generated HDL code is synthesized into
Virtex®-6 (XC6VLX240T-1FFG1156) FPGA, the design achieves 260 MHz clock frequency. It
uses the following resources.
Xilinx LogiCORE® DSP48
|Block RAM (16K)||0|
Performance of the synthesized HDL code varies depending on your target and synthesis options.