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Complex to Magnitude-Angle HDL Optimized

Compute magnitude and/or phase angle of complex signal—optimized for HDL code generation using the CORDIC algorithm


Math Operations



The Complex to Magnitude-Angle HDL Optimized block computes the magnitude and/or phase angle of a complex signal. It provides hardware-friendly control signals. The block uses a pipelined Coordinate Rotation Digital Computer (CORDIC) algorithm to achieve an efficient HDL implementation.

Signal Attributes

PortDirectionDescriptionData Type
dataInInputComplex scalar input data.

  • fixdt()

  • int32/16/8

  • uint32/16/8

double/single are allowed for simulation but not for HDL code generation.

validInInputIndicates that the input data is valid. When validIn is high, the block captures the dataIn value. boolean
magnitudeOutputScalar output data.Same as dataIn
angleOutputScalar output data. Optional. Same as dataIn
validOutOutputIndicates that the output data is valid. When the magnitude or angle output is ready, the block sets validOut high . boolean


Number of iterations source

Specifies the source of Number of iterations for the CORDIC algorithm. Select Auto to set the number of iterations to the input word length − 1. If the input is double or single, Auto sets the number of iterations to 16. Select Property to set the number of iterations from Number of iterations. The default is Auto.

Number of iterations

Specifies the number of CORDIC iterations the block executes. This parameter is visible only when Number of iterations source is set to Property. The number of iterations must be less than or equal to the input data word length − 1.

The latency of the block depends on the number of iterations performed. See Latency.

Output format

Specifies which output ports are active. You can select Magnitude, Angle, or Magnitude and angle. The default is Magnitude and angle.

Angle format

Specifies the format of the angle output. You can select Normalized or Radians. Select Normalized to return output in a fixed-point format that normalizes the angles in the range [–1,1]. For more information see Normalized Angle Format. Select Radians to return output as a fixed-point value between π and −π. The default format is Normalized.

Scale output

Scales output by the inverse of the CORDIC gain factor. The default value is selected.


If you turn off output scaling, and apply the CORDIC gain elsewhere in your design, you must exclude the π/4 term. The quadrant mapping algorithm replaces the first CORDIC iteration by mapping inputs onto the angle range [0,π/4]. Therefore, the initial rotation does not contribute a gain term.


If the input is 0+0i, the output angle is undefined. The block does not implement correction logic to force the output to 0. You can ignore this output angle.


CORDIC Algorithm

The CORDIC algorithm is a hardware-friendly method for performing trigonometric functions. It is an iterative algorithm that approximates the solution by converging toward the ideal point. The block uses CORDIC vectoring mode to iteratively rotate the input onto the real axis.

The Givens method for rotating a complex number x+iy by an angle θ is as follows. The direction of rotation, d, is +1 for counterclockwise and −1 for clockwise.


For a hardware implementation, factor out the cosθ to leave a tanθ term.


To rotate the vector onto the real axis, choose a series of rotations of θn so that tanθn=2n. Remove the cosθ term so each iterative rotation uses only shift and add operations.


Combine the missing cosθ terms from each iteration into a constant, and apply it with a single multiplier to the result of the final rotation. The output magnitude is the scaled final value of x. The output angle, z, is the sum of the rotation angles.


Modified CORDIC Algorithm

The convergence region for the standard CORDIC rotation is ≈±99.7°. To work around this limitation, before doing any rotation, the block maps the input into the [0,π/4] range using the following algorithm.

if abs(x) > abs(y) 
  input_mapped = [abs(x), abs(y)];
  input_mapped = [abs(y), abs(x)];
At each iteration, the block rotates the vector towards the real axis. The rotation is counterclockwise when y is negative, and clockwise when y is positive.

Quadrant mapping saves hardware resources and reduces latency by reducing the number of CORDIC pipeline stages by one. The CORDIC gain factor, Kn, therefore does not include the n=0, or cos(π/4) term.


After the CORDIC iterations are complete, the block corrects the angle back to its original location. First it adjusts the angle to the correct side of π/4.

if abs(x) > abs(y)
  angle_unmapped = CORDIC_out;
  angle_unmapped = (pi/2) - CORDIC_out;
Then it flips the angle to the original quadrant.
if (x < 0) 
  if (y < 0)
    output_angle = - pi + angle_unmapped;
    output_angle = pi - angle_unmapped;
  if (y<0)
    output_angle = -angle_unmapped;


The block generates a pipelined HDL architecture to maximize throughput. Each CORDIC iteration is done in one pipeline stage. The gain multiplier, if enabled, is implemented with Canonical Signed Digit (CSD) logic.

Input Word LengthOutput Magnitude Word Length

Input Word LengthOutput Angle Word Length
fixdt([ ],WL,FL)Radiansfixdt(1,WL+3,WL)

The CORDIC logic at each pipeline stage implements one iteration. For each pipeline stage, the shift and angle rotation are constants.

When you set Output format to Magnitude, the block does not generate HDL code for the angle accumulation and quadrant correction logic.

Normalized Angle Format

This format normalizes the fixed-point radian angle values around the unit circle. This is a more efficient use of bits than a range of [0,2π] radians. Normalized angle format also enables wraparound at 0/2π without additional detect and correct logic.

For example, representing the angle with 3 bits results in the following normalized values.

Using the mapping described in Modified CORDIC Algorithm, the block normalizes the angles across [0,π/4] and maps them to the correct octant at the end of the calculation.

Control Signals

The validIn signal qualifies the input data. When the output data calculated from a valid input reaches the end of the pipeline, the block asserts the validOut signal.


The output is valid Number of iterations + 2 cycles after valid input.

When you set Number of iterations source to Property, the block shows the latency immediately. When you set Number of iterations source to Auto, the block calculates the latency based on the input port data type, and displays it when you update the model.

When you set Number of iterations source to Auto, the number of iterations is input word length − 1, and the latency is input word length + 1. If the input is double or single type, the number of iterations is 16, and the latency is 18.

HDL Code Generation

This block supports HDL code generation using HDL Coder™. HDL Coder provides additional configuration options that affect HDL implementation and synthesized logic. For more information on implementations, properties, and restrictions for HDL code generation, see Complex to Magnitude-Angle HDL Optimized in the HDL Coder documentation.


Performance was measured for the default configuration, with output scaling disabled and fixdt(1,16,12) input. When the generated HDL code is synthesized into a Xilinx® Virtex®-6 (XC6VLX240T-1FFG1156) FPGA, the design achieves 260 MHz clock frequency. It uses the following resources.

ResourceNumber Used

Xilinx LogiCORE® DSP48

Block RAM (16K)0

Performance of the synthesized HDL code varies depending on your target and synthesis options.

Introduced in R2014b

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