Note: This page has been translated by MathWorks. Please click here

To view all translated materials including this page, select Japan from the country navigator on the bottom of this page.

To view all translated materials including this page, select Japan from the country navigator on the bottom of this page.

Finite impulse response filter—optimized for HDL code generation

**Library:**DSP System Toolbox / Filtering / Filter Implementations

DSP System Toolbox HDL Support / Filtering

The Discrete FIR Filter HDL Optimized block models FIR filter architectures optimized for HDL code generation. The block is sample based, accepting one scalar at a time. It provides a hardware-friendly interface with optional input and output flow control signals.

The block implements a direct-form systolic FIR filter architecture based on multiply-accumulate operations with pipeline registers. The choice of architecture makes the block well-suited for high-throughput HDL code generation targeted for FPGAs with dedicated DSP blocks. The generated HDL code runs at a high clock rate and can filter new input data on every cycle.

The block provides flexible and efficient resource sharing options.
This property results in tradeoffs between throughput and resource
utilization. A sharing factor of * N* indicates
that the block reduces overall DSP resource utilization by a factor
of

`N`

`N`

To provide a cycle-accurate simulation of the generated HDL code, the block models pipeline registers and resource sharing. These operations cause a delay between valid input data and the corresponding valid output data. The actual latency depends on the number of coefficients and the sharing factor.

Was this topic helpful?