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Discrete FIR Filter HDL Optimized

Finite impulse response filter—optimized for HDL code generation

  • Library:
  • DSP System Toolbox / Filtering / Filter Implementations

    DSP System Toolbox HDL Support / Filtering

Description

The Discrete FIR Filter HDL Optimized block models FIR filter architectures optimized for HDL code generation. The block is sample based, accepting one scalar at a time. It provides a hardware-friendly interface with optional input and output flow control signals.

The block implements a direct-form systolic FIR filter architecture based on multiply-accumulate operations with pipeline registers. The choice of architecture makes the block well-suited for high-throughput HDL code generation targeted for FPGAs with dedicated DSP blocks. The generated HDL code runs at a high clock rate and can filter new input data on every cycle.

The block provides flexible and efficient resource sharing options. This property results in tradeoffs between throughput and resource utilization. A sharing factor of N indicates that the block reduces overall DSP resource utilization by a factor of N. In this case, the block can process only input samples that are at least N cycles apart. To determine when the block is ready for new input data, use the optional ready output port.

To provide a cycle-accurate simulation of the generated HDL code, the block models pipeline registers and resource sharing. These operations cause a delay between valid input data and the corresponding valid output data. The actual latency depends on the number of coefficients and the sharing factor.

Ports

Input

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Input data, specified as a real or complex scalar. When the input data type is integer or fixed point, the block uses fixed-point arithmetic for internal calculations. double and single are accepted for simulation but not for HDL code generation.

Data Types: fixed point | single | double | int8 | int16 | int32 | uint8 | uint16 | uint32
Complex Number Support: Yes

When validIn is true, the block captures the input data on dataIn. The port is enabled by default and is required when you select DSP resource sharing.

Dependencies

To enable this port, on the Main tab, select Share DSP resources. Alternatively, if you clear Share DSP resources, you can enable this port by selecting Enable valid input port on the Control Ports tab.

Data Types: Boolean

Output

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Filtered output data, returned as a real or complex scalar. When the input data type is floating point, the output data inherits the data type of the input data. When the input data is integer or fixed point, the Output parameter on the Data Types tab controls the output data type.

Data Types: fixed point | single | double
Complex Number Support: Yes

The block sets validOut to true with each valid output data returned by dataOut.

Data Types: Boolean

The block sets ready to true to indicate that it is ready for new input data on the next cycle.

Dependencies

To enable this port, on the Control Port tab, select Enable ready output port.

Data Types: Boolean

Parameters

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Main

Discrete FIR filter coefficients, specified as a vector of numeric values. You can also specify the vector as a workspace variable, or as a call to a filter design function. Complex coefficients are not supported. When the input data type is floating point, the block casts the coefficients to the same data type as the input. When the input data type is integer or fixed point, you can modify coefficient type casting details by setting the Coefficients on the Data Types tab.

Data Types: single | double | int8 | int16 | int32 | uint8 | uint16 | uint32

Enable resource sharing to reduce overall DSP resource utilization on the FPGA. When this parameter is selected, specify the Sharing factor by which you want to reduce the number of DSPs.

Factor by which the number of DSPs is reduced, specified as a positive integer. A sharing factor of N indicates that the block reduces DSP resource utilization by a factor of N. In this case, the block can process only input samples that are at least N cycles apart.

Dependencies

To enable this parameter, on the Main tab, select Share DSP resources.

Data Types

Rounding mode for type casting the output to the data type specified by Output. When the input data type is floating point, the value of Rounding mode has no effect. See Rounding Modes for more details.

Overflow handling for type casting the output to the data type specified by Output. When the input data type is floating point, the value of Saturate on integer overflow has no effect. See Overflow Handling for more details.

The block casts the filter coefficients of the discrete FIR filter to this data type. The quantization uses nearest rounding and saturate overflow modes. When the input data type is floating point, the value of Coefficients has no effect.

The block casts the output of the discrete FIR filter to this data type. The quantization uses the settings of Rounding mode and Overflow mode. When the input data type is floating point, the value of the Output data type has no effect.

Control Ports

Select this parameter to enable the validIn port.

Dependencies

To enable this parameter, on the Main tab, clear Share DSP resources. When DSP resources are shared, the validIn port always shows.

Select this parameter to enable the ready port.

Algorithms

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The block implements a direct-form systolic FIR filter architecture based on multiply-accumulate operations with pipeline registers. The simulation models the latency incurred by the pipeline registers of the generated HDL code, so that the latency of the block matches the hardware.

The transfer function has L coefficients. The sharing factor, N, and the target device determine the specifics of the architecture used for simulation and HDL code generation. The implementation takes into account vendor-specific hardware details of the DSP blocks when adding pipeline registers to the architecture. The following diagrams depict the differences between the architecture choices made for FPGA targets from two different hardware vendors.

Introduced in R2017a

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