Multiphase Clock

Generate multiple binary clock signals

Library

  • Sources

    dspsrcs4

  • Signal Management / Switches and Counters

    dspswit3

Description

The Multiphase Clock block generates a 1-by-N vector of clock signals, where you specify the integer N in the Number of phases parameter. Each of the N phases has the same frequency, f, specified in hertz by the Clock frequency parameter.

The clock signal indexed by the Starting phase parameter is the first to become active, at t=0. The other signals in the output vector become active in turn, each one lagging the preceding signal's activation by 1/(N*f) seconds, the phase interval. The period of the output is therefore 1/(N*f) seconds.

The active level can be either high (1) or low (0), as specified by the Active level (polarity) parameter. The duration of the active level, D, is set by the Number of phase intervals over which the clock is active. This value, which can be an integer value between 1 and N-1, specifies the number of phase intervals that each signal should remain in the active state after becoming active. The active duty cycle of the signal is D/N.

Examples

In the following ex_multiphaseclock_refex_multiphaseclock_ref model, the Multiphase Clock block generates a 100 Hz five-phase output in which the third signal is first to become active. The block uses a high active level with a duration of one interval.

The Scope window below shows the Multiphase Clock block's output. Note that the first active level appears at t=0 on y(3), the second active level appears at t=0.002 on y(4), the third active level appears at t=0.004 on y(5), the fourth active level appears at t=0.006 on y(1), and the fifth active level appears at t=0.008 on y(2). Each signal becomes active 1/(5*100) seconds after the previous signal.

To experiment further, try changing the Number of phase intervals over which clock is active setting to 3 so that the active-level duration is three phase intervals (60% duty cycle).

Dialog Box

Clock frequency

The frequency of all output clock signals.

Number of phases

The number of different phases, N, in the output vector.

Starting phase

The vector index of the output signal to first become active.

Number of phase intervals over which clock is active

The duration of the active level for every output signal.

Active level

The active level, High (1) or Low (0).

Output data type

The output data type.

Supported Data Types

  • Double-precision floating point

  • Single-precision floating point

  • Boolean

See Also

ClockSimulink
CounterDSP System Toolbox
Pulse GeneratorSimulink
Event-Count ComparatorDSP System Toolbox

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