Generate real or complex sinusoidal signals—optimized for HDL code generation

Signal Operations

`dspsigops`

Sources

`dspsrcs4`

The block appears in `dspsigops`

with **Phase
increment Source** parameter set to `Input port`

.

In addition, the block also appears in `dspsrsc4`

library
with **Phase increment Source** parameter set to `Property`

.

The NCO HDL Optimized block generates real or complex sinusoidal signals, while providing hardware-friendly control signals. It uses the same phase accumulation and lookup table technology as implemented in the NCO block. It provides the following features:

A lookup table compression option to reduce the lookup table size with less than one LSB loss in precision. See Lookup Table Algorithm for more detail.

An option to synthesize the lookup table to a ROM when using HDL Coder™ with an FPGA target. To enable this feature, right-click the block, select

**HDL Code > HDL Block Properties**and set**LUTRegisterResetType**to`none`

.An optional input port for external dither.

An optional reset port that triggers a reset of the phase to its initial value during the sinusoid output generation.

An optional output port for the current NCO phase.

The following image illustrates the port signals of the interface for the NCO HDL Optimized block.

The following table provides the descriptions of the port signals.

Port | Direction | Description | Data Type |
---|---|---|---|

`inc` | Input | Phase increment source when you select input port | Scalar integer of type int32/16/8, uint32/16/8, fixdt([],N,0) |

`offset` | Input | Phase offset source when you select input port | Scalar integer of type int32/16/8, uint32/16/8, fixdt([],N,0) |

`dither` | Input | Dither source when you select input port | Scalar integer of type int32/16/8, uint32/16/8, fixdt([],N,0) |

`reset` | Input | Reset the accumulator to zero | Boolean |

`validIn` | Input | Increment the phase when `validIn` input is
high. When `validIn` is low, the phase is held. | Boolean |

`Sin` | Output | Generated sine output | Double/single/signed binary point scaling |

`Cos` | Output | Generated cosine output | Double/single/signed binary point scaling |

`phase` | Output | Current phase of NCO | fixdt(1,M,0). M is the quantized accumulator bits. |

`validOut` | Output | `validOut` indicates whether the data output
is valid or not. When `validOut` is high, the data
output is valid. When `validOut` is low, the data
output is not valid. | Boolean |

**Phase increment source**Defines how you specify the phase increment. You can set the phase increment with an input port or you can enter a value in the dialog box. The default value is

`Input port`

. If you select`Property`

, the**Phase increment**parameter appears in the dialog box.**Phase increment**Specify the phase increment. The default value is 100. This value is scalar.

This parameter is visible when you set

**Phase increment source**to`Property`

.**Phase offset source**Defines how you specify the phase offset. You can set the phase offset from an input port or from the dialog box. The default value is

`Property`

. If you select`Input port`

, the offset port appears on the block icon.**Phase offset**Specify the phase offset. The default value is 0. This value is scalar. You can use integer data types, including fixed-point data types with zero fraction length.

This parameter is visible when you set

**Phase offset source**to`Property`

.**Dither source**Defines how you specify the dither. The default value is

`Property`

. You can set the dither from an input port or from the dialog box. If you select`Property`

, the**Number of dither bits**parameter appears in the dialog box. If you select`Input port`

, a port appears on the block. If you select`None`

, the block does not add dither.**Number of dither bits**Specify the dither bits. The default value is 4. This value must be a positive integer.

This option is visible when you set

**Dither source**to`Property`

.**Quantize phase**Select to enable quantization of the accumulated phase. The default value is selected.

When you select

**Quantize phase**, the**Number of quantizer accumulator bits**parameter appears.**Number of quantizer accumulator bits**Specify the number of quantized accumulator bits. The default value is 12. This parameter determines the number of entries needed in the lookup table of sine values. The number of quantized accumulator bits must be less than the accumulator word length.

This parameter is visible only if you select

**Quantize phase**.**Enable lookup table compression method**Compress the lookup table when selected. The default value is not selected.

**Enable reset input port**Reset the accumulator to 0 when selected. The default value is not selected.

**Type of output signal**Choose whether the block output is

`Sine`

,`Cosine`

,`Complex exponential`

, or`Sine and cosine`

signals. If you select complex exponential, the output is of the form`sine + j*cosine`

. If you select`Sine and cosine`

, the sine and cosine values are sent out on different ports. The default is`Sine`

.**Show phase port**Output the current phase when selected. The default is not selected.

**Simulate using**Type of simulation to run. This parameter does not affect generated HDL code.

`Code generation`

(default)Simulate model using generated C code. The first time you run a simulation, Simulink

^{®}generates C code for the block. The C code is reused for subsequent simulations, as long as the model does not change. This option requires additional startup time but provides faster simulation speed than`Interpreted execution`

.`Interpreted execution`

Simulate model using the MATLAB

^{®}interpreter. This option shortens startup time but has slower simulation speed than`Code generation`

.

**Rounding Mode**The rounding mode when inputs are fixed point is

`Floor`

.**Overflow Mode**The overflow mode when inputs are fixed point is

`Wrap`

.- (Accumulator)
**Data Type** The output data type is

`Binary point scaling`

.- (Accumulator)
**Signed** The accumulator data type is signed.

- (Accumulator)
**Word length** Accumulator word length. Default value is 16.

- (Accumulator)
**Fraction length** Accumulator fraction length. Value is 0.

- (Output)
**Data Type** Select

`double`

,`single`

, or`Binary point scaling`

. The default is`Binary point scaling`

.If you select

`Binary point scaling`

, the parameters for output word length and fraction length appear. All output data types are signed.- (Output)
**Signed** All output data types are signed.

- (Output)
**Word length** Output word length. Default value is 16.

- (Output)
**Fraction length** Output fraction length. Default value is 14.

When you select lookup table (LUT) compression, the NCO HDL Optimized block applies the Sunderland compression method. Sunderland techniques use trigonometric identities to divide each phase of the quarter sine wave into three components and express it as:

$$\mathrm{sin}(A+B+C)=\mathrm{sin}(A+B)\mathrm{cos}C+\mathrm{cos}A\mathrm{cos}B\mathrm{cos}C-\mathrm{sin}A\mathrm{sin}B\mathrm{sin}C$$

If the phase has 12 bits, the components are defined as:

A , the four most significant bits

$$(0\le A\le \frac{\pi}{2})$$

B, the following four bits

$$(0\le B\le \frac{\pi}{2}\times {2}^{-4})$$

C, the four least significant bits

$$(0\le C\le \frac{\pi}{2}\times {2}^{-}{}^{8})$$

Because C is small enough that sin(C)≅1 and cos(C)≅0 , the equation is approximated by:

$$\mathrm{sin}(A+B+C)\approx \mathrm{sin}(A+B)+\mathrm{cos}A\mathrm{sin}C$$

The NCO HDL Optimized block implements this equation
with one LUT for sin(A+B) and one LUT for cos(A)sin(C). The second
term is a fine correction factor that you can truncate to fewer bits
without losing precision. With the default accumulator size of 16
bits, and the example phase width of 12 bits, the LUTs use only 2^{8}×16
plus 2^{8}×4 bits (5kb). A quarter sine
lookup table would use 2^{12}×16 bits
(65kb). This approximation is accurate within 1 LSB which gives an
SNR of at least 60 dB on the output. See L.
Cordesses, "Direct Digital Synthesis: A Tool for Periodic Wave Generation
(Part 1)", IEEE Signal Processing Magazine, DSP Tips & Tricks
column, pp. 50–54, Vol. 21, No. 4 July 2004.

There are two input control signals, `reset`

and `validIn`

,
and one output control signal, `validOut`

. When `reset`

is
high, the block sets the phase accumulator to zero. When `validIn`

is
high, the block increments the phase. When `validIn`

is
low, the block stops the phase accumulator and holds its state. When `validOut`

is
high, the output is valid.

The latency of the NCO HDL Optimized block is 6 cycles.

This block supports HDL code generation using HDL Coder. HDL Coder provides additional configuration options that affect HDL implementation and synthesized logic. For more information on implementations, properties, and restrictions for HDL code generation, see NCO HDL Optimized in the HDL Coder documentation.

Was this topic helpful?