Generate real or complex sinusoidal signals—optimized for HDL code generation
Signal Operations
dspsigops
Sources
dspsrcs4
Note:

The NCO HDL Optimized block generates real or complex sinusoidal signals, while providing hardwarefriendly control signals. It uses the same phase accumulation and lookup table technology as implemented in the NCO block. It provides the following features:
A lookup table compression option to reduce the lookup table size with less than one LSB loss in precision. See Lookup Table Algorithm for more detail.
An option to synthesize the lookup table to a ROM
when using HDL Coder™ with an FPGA target. To enable this feature,
rightclick the block, select HDL Code > HDL Block
Properties and set LUTRegisterResetType to none
.
An optional input port for external dither.
An optional reset port that triggers a reset of the phase to its initial value during the sinusoid output generation.
An optional output port for the current NCO phase.
This icon shows all the possible ports of the NCO HDL Optimized block.
Port  Direction  Description  Data Type 

inc  Input  Optional. Phase increment, specified as a scalar integer. 
double and single are
allowed for simulation but not for HDL code generation. 
offset  Input  Optional. Phase offset, specified as a scalar integer. 
double and single are
allowed for simulation but not for HDL code generation. 
dither  Input  Optional. Dither, specified as a scalar integer. 
double and single are
allowed for simulation but not for HDL code generation. 
reset  Input  Optional. Reset the accumulator to zero when reset is
high.  boolean 
validIn  Input  Optional. Increment the phase when validIn is true .
When validIn is false , the phase
is held.  boolean 
sin , cos , exp  Output  Generated waveform, returned as a scalar value. By default,
the output is a sine wave, sin . The port labels
change based on your selection for Type of output signal. 
double and single are
allowed for simulation but not for HDL code generation. 
phase  Output  Optional. Current phase of NCO, returned as a scalar value.  fixdt(1,M,Z) , where M is the number of
quantized accumulator bits, and Z is the accumulator word length. 
validOut  Output  Whether the data output is valid or not. When validOut is true ,
the data output is valid. When validOut is false ,
the data output is not valid.  boolean 
Note:
This block supports 
Defines how you specify the phase increment. You can set the
phase increment with an input port or you can enter a value for the
parameter. The default value is Input port
.
If you select Property
, the Phase
increment parameter appears.
Specify the phase increment. The default value is 100. This value is scalar.
This parameter is visible when you set Phase increment
source to Property
.
Defines how you specify the phase offset. You can set the phase
offset from an input port or from a parameter. The default value is Property
.
If you select Input port
, the offset port
appears on the block icon.
Specify the phase offset. The default value is 0. This value is scalar. You can use integer data types, including fixedpoint data types with zero fraction length.
This parameter is visible when you set Phase offset
source to Property
.
Defines how you specify the dither. The default value is Property
.
You can set the dither from an input port or from a parameter. If
you select Property
, the Number
of dither bits parameter appears. If you select Input
port
, a port appears on the block. If you select None
,
the block does not add dither.
Specify the dither bits. The default value is 4. This value must be a positive integer.
This option is visible when you set Dither source to Property
.
Select to enable quantization of the accumulated phase. The default value is selected.
When you select Quantize phase, the Number of quantizer accumulator bits parameter appears.
Specify the number of quantized accumulator bits. The default value is 12. This parameter determines the number of entries needed in the lookup table of sine values. The number of quantized accumulator bits must be less than the accumulator word length.
This parameter is visible only if you select Quantize phase.
Compress the lookup table when selected. The default value is not selected.
When selected, the reset
port is present
on the block icon. When reset
is high, the block
resets the accumulator to zero. The default value is not selected.
When selected, the validIn
port is present
on the block icon. When validIn
is true
,
the block increments the phase. When validIn
is false
,
the phase is held. The default value is selected.
Choose whether the block output signal is Sine
, Cosine
, Complex
exponential
, or Sine and cosine
.
If you select Complex exponential
, the
output is of the form sine + j*cosine
and the port
is labeled exp
. If you select Sine
and cosine
, the block shows two ports, sin
and cos
.
The default is Sine
.
Output the current phase when selected. The default is not selected.
The rounding
mode when inputs are fixed point is Floor
.
The overflow
mode when inputs are fixed point is Wrap
.
The output data type is Binary point scaling
.
The accumulator data type is signed.
Accumulator word length. Default value is 16.
Accumulator fraction length. Value is 0.
Select double
, single
,
or Binary point scaling
. The default is Binary
point scaling
.
If you select Binary point scaling
,
the parameters for output word length and fraction length appear.
All output data types are signed.
All output data types are signed.
Output word length. Default value is 16.
Output fraction length. Default value is 14.
When you select lookup table (LUT) compression, the NCO HDL Optimized block applies the Sunderland compression method. Sunderland techniques use trigonometric identities to divide each phase of the quarter sine wave into three components and express it as:
$$\mathrm{sin}(A+B+C)=\mathrm{sin}(A+B)\mathrm{cos}C+\mathrm{cos}A\mathrm{cos}B\mathrm{cos}C\mathrm{sin}A\mathrm{sin}B\mathrm{sin}C$$
If the phase has 12 bits, the components are defined as:
A, the four most significant bits
$$(0\le A\le \frac{\pi}{2})$$
B, the following four bits
$$(0\le B\le \frac{\pi}{2}\times {2}^{4})$$
C, the four least significant bits
$$(0\le C\le \frac{\pi}{2}\times {2}^{}{}^{8})$$
Because C is small enough that sin(C)≅1 and cos(C)≅0, the equation is approximated by:
$$\mathrm{sin}(A+B+C)\approx \mathrm{sin}(A+B)+\mathrm{cos}A\mathrm{sin}C$$
The NCO HDL Optimized block implements this equation with one LUT for sin(A+B) and one LUT for cos(A)sin(C). The second term is a fine correction factor that you can truncate to fewer bits without losing precision. With the default accumulator size of 16 bits, and the example phase width of 12 bits, the LUTs use only 2^{8}×16 plus 2^{8}×4 bits (5kb). A quarter sine lookup table would use 2^{12}×16 bits (65kb). This approximation is accurate within 1 LSB which gives an SNR of at least 60 dB on the output. See L. Cordesses, "Direct Digital Synthesis: A Tool for Periodic Wave Generation (Part 1)", IEEE Signal Processing Magazine, DSP Tips & Tricks column, pp. 50–54, Vol. 21, No. 4 July 2004.
There are two input control signals, reset
and validIn
,
and one output control signal, validOut
. When reset
is
high, the block sets the phase accumulator to zero. When validIn
is
high, the block increments the phase. When validIn
is
low, the block stops the phase accumulator and holds its state. When validOut
is
high, the output is valid.
The latency of the NCO HDL Optimized block is 6 cycles.
This block supports HDL code generation using HDL Coder. HDL Coder provides additional configuration options that affect HDL implementation and synthesized logic. For more information on implementations, properties, and restrictions for HDL code generation, see NCO HDL Optimized in the HDL Coder documentation.