step

Class: hdlram

Read or write input value to memory location

    Note:   hdlram has been renamed. Use hdl.RAM instead.

Syntax

DATAOUT = step(H,WRITEDATA,READWRITEADDRESS,WRITEENABLE)
READDATAOUT = step(H,WRITEDATA,WRITEADDRESS,WRITEENABLE,READADDRESS)
[WRITEDATAOUT,READDATAOUT] = step(H,WRITEDATA,WRITEADDRESS,WRITEENABLE,READADDRESS)

Description

DATAOUT = step(H,WRITEDATA,READWRITEADDRESS,WRITEENABLE) allows you to read the value in memory location READWRITEADDRESS when WRITEENABLE is false. It also allows you to write the value WRITEDATA into the memory location READWRITEADDRESS when WRITEENABLE is true. DATAOUT is the new or old data at READWRITEADDRESS when WRITEENABLE is true, or the data at READWRITEADDRESS when WRITEENABLE is false. This step syntax is appropriate for a single-port RAM System object™.

READDATAOUT = step(H,WRITEDATA,WRITEADDRESS,WRITEENABLE,READADDRESS) allows you to write the value WRITEDATA into memory location WRITEADDRESS when WRITEENABLE is true. READDATAOUT is the old data at the address location READADDRESS. This step syntax is appropriate for a simple dual-port RAM System object.

[WRITEDATAOUT,READDATAOUT] = step(H,WRITEDATA,WRITEADDRESS,WRITEENABLE,READADDRESS) allows you to write the value WRITEDATA into the memory location WRITEADDRESS when WRITEENABLE is true. WRITEDATAOUT is the new or old data at memory location WRITEADDRESS. READDATAOUT is the old data at the address location READADDRES. This step syntax is appropriate for a dual-port RAM System object.

hdlram Input Requirements

InputRequirement
WRITEDATA Must be scalar. This value can be double, single, integer, or a fixed-point (fi) object, and can be real or complex.
WRITEENABLE Must be a scalar, logical value.
WRITEADDRESS and READADDRESSMust be real and unsigned. This value can be either fixed-point (fi) objects or integers.

Examples

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Read/Write Single-Port RAM

Create System object that can write to a single port RAM and read the newly written value out.

Construct single-port RAM System object.

hRAM = hdlram('RAMType','Single port','WriteOutputValue','New data');

Preallocate memory.

dataLength    = 100;
[dataIn dataOut] = deal(zeros(1,dataLength));

Write randomly generated data to the System object, and then read data back out again.

for ii = 1:dataLength
  dataIn(ii)  = randi([0 63],1,1,'uint8');
  addressIn   = uint8(ii-1);
  writeEnable = true;
  dataOut(ii) = step(hRAM,dataIn(ii),addressIn,writeEnable);
end ;
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