This example shows how to work with MATLAB HDL Coder™ projects to generate HDL from MATLAB designs.
This example helps you familiarize yourself with the following aspects of HDL code generation:
Generating HDL code from MATLAB design.
Generating a HDL test bench from a MATLAB test bench.
Verifying the generated HDL code using a HDL simulator.
Synthesizing the generated HDL code using a HDL synthesis tool.
The MATLAB code used in this example implements a simple symmetric FIR filter. This example also shows a MATLAB test bench that exercises the filter.
design_name = 'mlhdlc_sfir.m'; testbench_name = 'mlhdlc_sfir_tb.m';
Execute the following lines of code to copy the necessary example files into a temporary folder.
mlhdlc_demo_dir = fullfile(matlabroot, 'toolbox', 'hdlcoder', 'hdlcoderdemos', 'matlabhdlcoderdemos'); mlhdlc_temp_dir = [tempdir 'mlhdlc_sfir']; % Create a temporary folder and copy the MATLAB files. cd(tempdir); [~, ~, ~] = rmdir(mlhdlc_temp_dir, 's'); mkdir(mlhdlc_temp_dir); cd(mlhdlc_temp_dir); copyfile(fullfile(mlhdlc_demo_dir, design_name), mlhdlc_temp_dir); copyfile(fullfile(mlhdlc_demo_dir, testbench_name), mlhdlc_temp_dir);
Simulate the design with the test bench prior to code generation to make sure there are no runtime errors.
To create a new project, enter the following command:
coder -hdlcoder -new mlhdlc_sfir
Next, add the file 'mlhdlc_sfir.m' to the project as the MATLAB Function and 'mlhdlc_sfir_tb.m' as the MATLAB Test Bench.
You can refer to Getting Started with MATLAB to HDL Workflow tutorial for a more complete introduction to creating and populating HDL Coder projects.
Right-click the 'Float-to-Fixed Workflow' step and choose the option 'Run this task' to run all the steps to generate fixed-point MATLAB code.
Examine the generated fixed-point MATLAB code by clicking the links in the log window to open the MATLAB code in the editor.
For more details on fixed-point conversion, refer to the Floating-Point to Fixed-Point Conversion tutorial.
This step generates Verilog code from the generated fixed-point MATLAB design, and a Verilog test bench from the MATLAB test bench wrapper.
To set code generation options and generate HDL code:
Click the 'Code Generation' step to view the HDL code generation options panel.
In the Target tab, choose 'Verilog' as the 'Language' option.
Select the 'Generate HDL' and 'Generate HDL test bench' options.
In the Test bench tab, choose the 'Multi-file test bench' option to generate test bench code and test bench data (stimulus and response) in separate files.
In the 'Optimizations' tab, choose '1' as the Input and Output pipeline length, and enable the 'Distribute pipeline registers' option.
In the 'Coding style' tab, choose 'Include MATLAB source code as comments' and 'Generate report' to generate a code generation report with comments and traceability links.
Click the 'Run' button to generate both the Verilog design and testbench with reports.
Examine the log window and click the links to explore the generated code and the reports.
HDL Coder automates the process of running the generated HDL test bench using the ModelSim or ISIM™ simulator, and reports if the generated HDL simulation matches the numerics and latency with respect to the fixed-point MATLAB simulation.
HDL Coder also creates a Xilinx ISE™ or Altera Quartus™ project with the selected options and runs the selected logic synthesis and place-and-route steps for the generated HDL code.
Examine the log window to view the results of synthesis steps.
Run the following commands to clean up the temporary project folder.
mlhdlc_demo_dir = fullfile(matlabroot, 'toolbox', 'hdlcoder', 'hdlcoderdemos', 'matlabhdlcoderdemos'); mlhdlc_temp_dir = [tempdir 'mlhdlc_sfir']; clear mex; cd (mlhdlc_demo_dir); rmdir(mlhdlc_temp_dir, 's');