This example shows how to generate HDL code from MATLAB design implementing an bisection algorithm to calculate the square root of a number in fixed point notation.
Same implementation, originally using n-multipliers in HDL code, for wordlength n, under sharing, and streaming optimizations can generate HDL code only 1 multiplier, demonstrating the power of MATLAB HDL Coder optimizations.
The design of the square-root algorithm shows the pipelining concepts to achieve a fast clock rate in resulting RTL design.Since the design is already in fixed point, you don't need to run fixed-point conversion.
% Design Sqrt design_name = 'mlhdlc_sqrt.m'; % Test Bench for Sqrt testbench_name = 'mlhdlc_sqrt_tb.m';
Lets look at the Sqrt Design
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % MATLAB design: Pipelined Bisection Square root algorithm % % Introduction: % % Implement SQRT by the bisection algorithm in a pipeline, for unsigned fixed % point numbers (also why you don't need to run fixed-point conversion for this design). % The demo illustrates the usage of a pipelined implementation for numerical algorithms. % % Key Design pattern covered in this example: % (1) State of the bisection algorithm is maintained with persistent variables % (2) Stages of the bisection algorithm are implemented in a pipeline % (3) Code is written in a parameterized fashion, i.e. word-length independent, to work for any size fi-type % % Ref. 1. R. W. Hamming, "Numerical Methods for Scientists and Engineers," 2nd, Ed, pp 67-69. ISBN-13: 978-0486652412. % 2. Bisection method, http://en.wikipedia.org/wiki/Bisection_method, (accessed 02/18/13). % % Copyright 2013 The MathWorks, Inc. %#codegen function [y,z] = mlhdlc_sqrt( x ) persistent sqrt_pipe persistent in_pipe if isempty(sqrt_pipe) sqrt_pipe = fi(zeros(1,x.WordLength),numerictype(x)); in_pipe = fi(zeros(1,x.WordLength),numerictype(x)); end % Extract the outputs from pipeline y = sqrt_pipe(x.WordLength); z = in_pipe(x.WordLength); % for analysis purposes you can calculate the error between the fixed-point bisection routine and the floating point result. %Q = [double(y).^2, double(z)]; %[Q, diff(Q)] % work the pipeline for itr = x.WordLength-1:-1:1 % move pipeline forward in_pipe(itr+1) = in_pipe(itr); % guess the bits of the square-root solution from MSB to the LSB of word length sqrt_pipe(itr+1) = guess_and_update( sqrt_pipe(itr), in_pipe(itr+1), itr ); end %% Prime the pipeline % with new input and the guess in_pipe(1) = x; sqrt_pipe(1) = guess_and_update( fi(0,numerictype(x)), x, 1 ); %% optionally print state of the pipeline %disp('************** State of Pipeline **********************') %double([in_pipe; sqrt_pipe]) return end % Guess the bits of the square-root solution from MSB to the LSB in % a binary search-fashion. function update = guess_and_update( prev_guess, x, stage ) % Key step of the bisection algorithm is to set the bits guess = bitset( prev_guess, x.WordLength - stage + 1); % compare if the set bit is a candidate solution to retain or clear it if ( guess*guess <= x ) update = guess; else update = prev_guess; end return end
Execute the following lines of code to copy the necessary example files into a temporary folder.
mlhdlc_demo_dir = fullfile(matlabroot, 'toolbox', 'hdlcoder', 'hdlcoderdemos', 'matlabhdlcoderdemos'); mlhdlc_temp_dir = [tempdir 'mlhdlc_sqrt']; % create a temporary folder and copy the MATLAB files cd(tempdir); [~, ~, ~] = rmdir(mlhdlc_temp_dir, 's'); mkdir(mlhdlc_temp_dir); cd(mlhdlc_temp_dir); % copy files to the temp dir copyfile(fullfile(mlhdlc_demo_dir, design_name), mlhdlc_temp_dir); copyfile(fullfile(mlhdlc_demo_dir, testbench_name), mlhdlc_temp_dir);
It is always a good practice to simulate the design with the testbench prior to code generation to make sure there are no runtime errors.
ans = 1|0|0000000000 ans = 2|0|0000000000 ans = 3|0|0000000000 ans = 4|0|0000000000 ans = 5|0|0000000000 ans = 6|0|0000000000 ans = 7|0|0000000000 ans = 8|0|0000000000 ans = 9|0|0000000000 ans = 10|0|0000000000 ans = 11|0.53125|0001000100 ans = 12|0.54688|0001000110 ans = 13|0.5625|0001001000 ans = 14|0.64063|0001010010 ans = 15|0.92188|0001110110 ans = 16|0.92188|0001110110 ans = 17|1.0625|0010001000 ans = 18|1.125|0010010000 ans = 19|1.1875|0010011000 ans = 20|1.2344|0010011110 ans = 21|1.2813|0010100100 ans = 22|1.5781|0011001010 ans = 23|1.5781|0011001010 ans = 24|1.6875|0011011000 ans = 25|1.8438|0011101100 ans = 26|1.875|0011110000 ans = 27|1.9375|0011111000 ans = 28|1.9844|0011111110 ans = 29|2|0100000000 ans = 30|2.0781|0100001010 ans = 31|2.0938|0100001100 ans = 32|2.2031|0100011010 ans = 33|2.375|0100110000 ans = 34|2.4063|0100110100 ans = 35|2.4219|0100110110 ans = 36|2.4219|0100110110 ans = 37|2.4688|0100111100 ans = 38|2.5|0101000000 ans = 39|2.5156|0101000010 ans = 40|2.5156|0101000010 ans = 41|2.5781|0101001010 ans = 42|2.5938|0101001100 ans = 43|2.6094|0101001110 ans = 44|2.625|0101010000 ans = 45|2.6563|0101010100 ans = 46|2.6719|0101010110 ans = 47|2.6719|0101010110 ans = 48|2.7031|0101011010 ans = 49|2.7188|0101011100 ans = 50|2.75|0101100000
coder -hdlcoder -new mlhdlc_sqrt_prj
Next, add the file 'mlhdlc_sqrt.m' to the project as the MATLAB Function and 'mlhdlc_sqrt_tb.m' as the MATLAB Test Bench.
You can refer to Getting Started with MATLAB to HDL Workflow tutorial for a more complete tutorial on creating and populating MATLAB HDL Coder projects.
This design is already in fixed point and suitable for HDL code generation. It is not desirable to run floating point to fixed point advisor on this design.
Launch Workflow Advisor
Under 'Define Input Types' Choose 'Keep original types' for the option 'Fixed-point conversion'
Under 'Optimizations' tab in 'RAM Mapping' box uncheck 'MAP persistent variables to RAMs'. We don't want the pipeline to be inferred as a RAM.
Optionally you may want to choose, under 'Optimizations' tab, 'Area Optimizations' and set 'Resource sharing factor' equal to wordlength (10 here), select 'Stream Loops' under the 'Loop Optimizations' tab. Also don't forget to check 'Distributed Pipelining' when you enable the optimizations.
Click on the 'Code Generation' step and click 'Run'
Examine the generated HDL code by clicking on the hyperlinks in the Code Generation Log window.
Run the logic synthesis step with the following default options if you have ISE installed on your machine.
In the synthesis report, note the clock frequency reported by the synthesis tool without any optimization options enabled.
Typically timing performance of this design using Xilinx ISE synthesis tool for the 'Virtex7' chip family, device 'xc7v285t', speed grade -3, to be around 229MHz, and a maximum combinational path delay: 0.406ns.
Optimizations for this design (loop streaming and multiplier sharing) work to reduce resource usage, with a moderate trade-off on timing. For the particular word-length size in test bench you will see a reduction of n multipliers to 1.
You can run the following commands to clean up the temporary project folder.
mlhdlc_demo_dir = fullfile(matlabroot, 'toolbox', 'hdlcoder', 'hdlcoderdemos', 'matlabhdlcoderdemos'); mlhdlc_temp_dir = [tempdir 'mlhdlc_sqrt']; clear mex; cd (mlhdlc_demo_dir); rmdir(mlhdlc_temp_dir, 's');