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Getting Started with Hardware-Software Codesign Workflow for Xilinx Zynq Platform

This example shows how to use the HDL Coder™ to generate a custom HDL IP core which blinks LEDs on the Xilinx® Zynq® ZC702 evaluation kit, and shows how to use Embedded Coder® to generate C code that runs on the ARM® processor to control the LED blink frequency.

Introduction

This example is a step-by-step guide that helps introduce you to the hardware-software codesign workflow.

You can use MATLAB® and Simulink® to design, simulate, and verify your application, perform what-if scenarios with algorithms, and optimize parameters. You can then prepare your design for hardware and software implementation on the Zynq-7000 AP SoC by deciding which system elements will be performed by the programmable logic, and which system elements will run on the ARM Cortex-A9.

Using the guided workflow shown in this example, you automatically generate HDL code for the programmable logic using HDL Coder, generate C code for the ARM using Embedded Coder, and implement the design on the Xilinx Zynq Platform.

In this workflow, you perform the following steps:

  1. Set up your Zynq hardware and tools.

  2. Partition your design for hardware and software implementation.

  3. Generate an HDL IP core using HDL Workflow Advisor.

  4. Integrate the IP core into a Xilinx EDK project and program the Zynq hardware.

  5. Generate a software interface model.

  6. Generate C code from the software interface model and run it on the ARM Cortex-A9 processor.

  7. Tune parameters and capture results from the Zynq hardware using External Mode.

For more information, refer to other more advanced examples, and the HDL Coder and Embedded Coder documentation.

Requirements

  1. Xilinx ISE 14.7

  2. Xilinx Zynq-7000 SoC ZC702 Evaluation Kit

  3. HDL Coder Support Package for Xilinx Zynq-7000

  4. Embedded Coder Support Package for Xilinx Zynq-7000

Set up Zynq hardware and tools

1. Set up the Xilinx Zynq ZC702 evaluation kit as shown in the figure below. To learn more about the ZC702 hardware setup, please refer to Xilinx documentation.

1.1. Make sure your USB device drivers, such as for the Silicon Labs CP210x USB to UART Bridge, are installed correctly. If not, search for the drivers online and install them.

1.2. Make sure the SW16 switch is set as shown in the figure below, so you can boot Linux from the SD card.

1.3. Make sure the SW10 switch (JTAG chain input select two-position DIP switch) is set as shown in the figure below, so you can use the Digilent USB-to-JTAG interface (U23). Position 1: Off; Position 2: On.

1.4. Test the serial connection using the Zynq standard configuration. Baud rate: 115200; Data bits: 8; Stop bits: 1; Parity: None; Flow control: None.

1.5. Connect your computer and the Zynq board using an Ethernet cable. The default ZC702 IP address is 192.168.1.10. Set up the Ethernet network adapter on your computer to use an IP address on the same subnet, for example, 192.168.1.1. Set the subnet mask to 255.255.255.0. Make sure your computer and the Zynq board can ping each other.

2. Install the HDL Coder and Embedded Coder Support Packages for Xilinx Zynq-7000 if you haven't already. To start the installerinstaller, go to the MATLAB toolstrip and click Add-Ons > Get Hardware Support Packages. For more information, please refer to the Support Package Installation documentation.

3. Make sure you are using the SD card image provided by the Embedded Coder Support Package for Xilinx Zynq-7000. If you need to update your SD card image, run the Support Package Firmware UpdaterSupport Package Firmware Updater by running the following command at the MATLAB prompt:

targetupdater

4. Set up the Xilinx ISE synthesis tool path using the following command in the MATLAB command window. Use your own ISE installation path when you run the command.

hdlsetuptoolpath('ToolName', 'Xilinx ISE', 'ToolPath', 'C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\ise.exe');

5. Set up the Zynq hardware connection by entering the following commands in the MATLAB command window:

h = zynq();
h.setupZynqHardware();

The setupZynqHardware method logs in to the hardware via COM port and runs the ifconfig command to obtain the IP address of the board.

Partition your design for hardware and software implementation

The first step of the Zynq hardware-software codesign workflow is to decide which parts of your design to implement on the programmable logic, and which parts to run on the ARM processor.

Group all the blocks you want to implement on programmable logic into an atomic subsystem. This atomic subsystem is the boundary of your hardware-software partition. All the blocks inside this subsystem will be implemented on programmable logic, and all the blocks outside this subsystem will run on the ARM processor.

In this example, the subsystem led_counter is the hardware subsystem. It models a counter that blinks the LEDs on an FPGA board. Two input ports, Blink_frequency and Blink_direction, are control ports that determine the LED blink frequency and direction. All the blocks outside of the subsystem led_counter are for software implementation.

In Simulink, you can use the Slider Gain or Manual Switch block to adjust the input values of the hardware subsystem. In the embedded software, this means the ARM processor controls the generated IP core by writing to the AXI interface accessible registers. The output port of the hardware subsystem, LED, connects to the LED hardware. The output port, Read_Back, can be used to read data back to the processor.

open_system('hdlcoder_led_blinking');

Generate an HDL IP core using the HDL Workflow Advisor

Using the IP Core Generation workflow in the HDL Workflow Advisor enables you to automatically generate a sharable and reusable IP core module from a Simulink model. The generated IP core is designed to be connected to an embedded processor on an FPGA device. HDL Coder generates HDL code from the Simulink blocks, and also generates HDL code for the AXI interface logic connecting the IP core to the embedded processor. HDL Coder packages all the generated files into an IP core folder. You can then integrate the generated IP core with a larger FPGA embedded design in the Xilinx EDK environment.

1. Start the IP core generation workflow.

1.1. Open the HDL Workflow Advisor from the hdlcoder_led_blinking/led_counter subsystem by right-clicking the led_counter subsystem, and choosing HDL Code > HDL Workflow Advisor.

1.2. In the Set Target > Set Target Device and Synthesis Tool task, for Target workflow, select IP Core Generation.

1.3. For Target platform, select Xilinx Zynq ZC702 evaluation kit. If you don't have this option, select Get more to open the Support Package Installer. In the Support Package Installer, select Xilinx Zynq-7000 and follow the instructions provided by the Support Package Installer to complete the installation.

1.4. Click Run This Task to run the Set Target Device and Synthesis Tool task.

2. Configure the target interface.

Map each port in your DUT to one of the IP core target interfaces. In this example, input ports Blink_frequency and Blink_direction are mapped to the AXI4-Lite interface, so HDL Coder generates AXI interface accessible registers for them. The LED output port is mapped to an external interface, LEDs General Purpose [0:7], which connects to the LED hardware on the Zynq board.

2.1 In the Set Target > Set Target Interface task, choose AXI4-Lite for Blink_frequency, Blink_direction, and Read_back.

2.2 Choose LEDs General Purpose [0:7] for LED.

3. Generate the IP Core.

To generate the IP core, right-click the Generate RTL Code and IP Core task and select Run to Selected Task.

4. Generate and view the IP core report.

After you generate the custom IP core, the IP core files are in the ipcore folder within your project folder. An HTML custom IP core report is generated together with the custom IP core. The report describes the behavior and contents of the generated custom IP core.

Integrate the IP core with the Xilinx EDK environment

In this part of the workflow, you insert your generated IP core into a embedded system reference design, generate an FPGA bitstream, and download the bitstream to the Zynq hardware.

The reference design is a predefined Xilinx EDK project. It contains all the elements the Xilinx software needs to deploy your design to the Zynq platform, except for the custom IP core and embedded software that you generate.

1. To integrate with the Xilinx EDK environment, select the Create Project task under Embedded System Integration, and click Run This Task. A Xilinx PlanAhead project with EDK embedded design is generated, and a link to the project is provided in the dialog window. You can optionally open up the project to take a look.

2. If you have an Embedded Coder license, you can generate a software interface model in the next task, Generate Software Interface Model. The details of the software interface model are explained in the next section of this example, "Generate a software interface model".

3. Build the FPGA bitstream in the Build FPGA Bitstream task. Make sure the Run build process externally option is checked, so the Xilinx synthesis tool will run in a separate process from MATLAB. Wait for the synthesis tool process to finish running in the external command window.

4. After the bitstream is generated, select the Program Target Device task and click Run This Task to program the Zynq hardware.

After you program the FPGA hardware, the LED starts blinking on your Zynq board.

Next, you will generate C code to run on the ARM processor to control the LED blink frequency and direction.

Generate a software interface model

In the HDL Workflow Advisor, after you generate the IP core and insert it into the EDK reference design, you can optionally generate a software interface model in the Embedded System Integration > Generate Software Interface Model task.

The software interface model contains the part of your design that runs in software. It includes all the blocks outside of the HDL subsystem, and replaces the HDL subsystem with AXI driver blocks. If you have an Embedded Coder license, you can automatically generate embedded code from the software interface model, build it, and run the executable on Linux on the ARM processor. The generated embedded software includes AXI driver code, generated from the AXI driver blocks, that controls the HDL IP core.

Run the Generate Software Interface Model task and see that a new model is generated. The task dialog shows a link to the model.

In the generated software interface model, the "led_counter" subsystem is replaced with the AXI driver blocks which generate the interface logic between the ARM processor and FPGA.

Run the software interface model on Zynq ZC702 hardware

In this part of the workflow, you configure the generated software interface model, automatically generate embedded C code, and run your model on the ARM processor in the Zynq hardware in External mode.

When you are prototyping and developing an algorithm, it is useful to monitor and tune the algorithm while it runs on hardware. The External mode feature in Simulink enables this capability. In this mode, your algorithm is first deployed to the ARM processor in the Zynq hardware, and then linked with the Simulink model on the host computer through an Ethernet connection.

The main role of the Simulink model is to tune and monitor the algorithm running on the hardware. Because the ARM processor is connected to the HDL IP core through the AXI interface, you can use External mode to tune parameters, and capture data from the FPGA.

  1. In the generated model, open the Configuration Parameters dialog box.

  2. Select Solver and set "Stop Time" to "inf".

  3. From the model menu, select Simulation > Mode > External.

  4. Click the Run button on the model toolstrip. Embedded Coder builds the model, downloads the ARM executable to the Zynq ZC702 hardware, executes it, and connects the model to the executable running on the Zynq ZC702 hardware.

  5. Double-click the Slider Gain block. Change the Slider Gain value and observe the change in frequency of the LED array blinking on the Zynq ZC702 hardware. Double-click the Manual Switch block to switch the direction of the blinking LEDs.

  6. Double-click the scope connected to the Read_back output port and observe that the output data of the FPGA IP core is captured and sent back to the Simulink scope.

  7. When you are done changing model parameters, click the Stop button on the model. Observe that the system command window opened in the previous step indicates that the model has been stopped. At this point, you can close the system command window.

Summary

This example shows how the hardware and software codesign workflow helps automate the deployment of your MATLAB and Simulink design to a Zynq-7000 All Programmable SoC. You can explore the best ways to partition and deploy your design by iterating through the workflow.

The following diagram shows the high-level picture of the workflow you went through in this example. To learn more about the hardware and software codesign workflow, please refer to the HDL Coder documentationHDL Coder documentation.

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