This example shows how to use the HDL Workflow Advisor to generate a custom HDL IP core which blinks LEDs on Xilinx Zynq™ ZC702 evaluation kit, and how to use Embedded Coder to generate C code that runs on the ARM processor to control the LED blink frequency.
You can use MATLAB™ and Simulink™ to design, simulate, and verify your application, perform what-if scenarios with algorithms, and optimize parameters. You can then prepare your design for hardware and software implementation on the Zynq-7000 AP SoC by deciding which system elements will be performed by the programmable logic, and which system elements will run on the ARM Cortex-A9. Using the guided workflow shown in this example, you can automatically generate HDL code for the programmable logic using HDL Coder™, generate C code for the ARM using Embedded Coder™, and implement the design on the Xilinx Zynq Platform.
This example is a step-by-step guide that helps introduce you to the HW/SW codesign workflow. In this workflow, you perform the following steps:
Set up your Zynq hardware and tools.
Partition your design for hardware and software implementation.
Generate an HDL IP core using HDL Workflow Advisor.
Integrate the IP core into a Xilinx EDK project and program the Zynq hardware.
Generate a software interface model.
Generate C code from the software interface model and run it on the ARM Cortex-A9 processor.
Tune parameters and capture results from the Zynq hardware using External Mode.
For more information, refer to other more advanced examples, and the HDL Coder and Embedded Coder documentation.
Xilinx ISE 14.4
Xilinx Zynq-7000 SoC ZC702 Evaluation Kit running the Linux image in the Base Targeted Reference Design 14.4
HDL Coder™ Support Package for Xilinx Zynq™-7000
Embedded Coder™ Support Package for Xilinx Zynq™-7000
1. Set up the Xilinx Zynq ZC702 evaluation kit as shown in the figure below. Switch on the hardware using power switch.
Make sure your USB device drivers, such as Silicon Labs CP210x USB to UART Bridge, are installed correctly. If not, search for the drivers online and install them.
Comment out following line in the init.sh file in the SD card on your Zynq board to disable the default Xilinx Zynq Base TRD demo.
2. Set up the Xilinx ISE synthesis tool path using the following command in the MATLAB command window. Use your own ISE installation path when you run the command.
hdlsetuptoolpath('ToolName', 'Xilinx ISE', 'ToolPath', 'C:\Xilinx\14.4\ISE_DS\ISE\bin\nt64\ise.exe');
3. Set up the Zynq hardware connection by entering the following commands in the MATLAB command window:
h = zynq(); h.setupZynqHardware();
setupZynqHardware method logs into the hardware via COM port and runs ifconfig command to obtain the IP Address of the board.
4. Configure the embedded software build tools with the following steps:
4.2. Clear the Display operational configurations only checkbox.
4.3. Set Configuration to xilinx_ise_14_x.
4.4 Click Apply to save the settings.
Note: If you are performing this step for the first time after you install the support package, a folder browser pops up that asks you to point to the installation directory of Xilinx tools. Select the "ISE_DS" folder in the Xilinx tools installation directory tree. For example, C:\Xilinx\14.4\ISE_DS.
The first step of the Zynq HW/SW codesign workflow is to decide which parts of your design to implement on the programmable logic, and which parts to run on the ARM processor.
Group all the blocks you want to implement on programmable logic into an atomic subsystem. This atomic subsystem is the boundary of your hardware/software partition. All the blocks inside this subsystem will be implemented on programmable logic, and all the blocks outside this subsystem will run on the ARM processor.
In this example, the subsystem led_counter is the hardware subsystem. It models a counter that blinks the LEDs on an FPGA board. Two input ports, Blink_frequency and Blink_direction, are control ports that determine the LED blink frequency and direction. All the blocks outside of the subsystem led_counter are for software implementation.
In Simulink, you can use the Slider Gain or Manual Switch block to adjust the input values of the hardware subsystem. In the embedded software, this means the ARM processor controls the generated IP core by writing to the AXI interface accessible registers. The output port of the hardware subsystem, LED, connects to the LED hardware. The output port, Read_Back, can be used to read data back to the processor.
Using the IP Core Generation workflow in the HDL Workflow Advisor enables you to automatically generate a sharable and reusable IP core module from a Simulink model. The generated IP core is designed to be connected to an embedded processor on an FPGA device. HDL Coder™ generates HDL code from the Simulink blocks, and also generates HDL code for the AXI interface logic connecting the IP core to the embedded processor. HDL Coder™ packages all the generated files into an IP core folder. You can then integrate the generated IP core with a larger FPGA embedded design in the Xilinx EDK environment.
1. Start the IP core generation workflow.
1.1. Open the HDL Workflow Advisor from the hdlcoder_led_blinking/led_counter subsystem by right-clicking the led_counter subsystem, and choosing HDL Code > HDL Workflow Advisor.
1.2. In the Set Target > Set Target Device and Synthesis Tool task, for Target workflow, select IP Core Generation.
1.3. For Target platform, select Xilinx Zynq ZC702 evaluation kit. If you don't have this option, select Get more to open the Support Package Installer. In the Support Package Installer, select Xilinx Zynq-7000 and follow the instructions provided by the Support Package Installer to complete the installation.
2. Configure the target interface.
Map each port in your DUT to one of the IP core target interfaces. In this example, input ports Blink_frequency and Blink_direction are mapped to the AXI4-Lite interface, so HDL Coder™ generates AXI interface accessible registers for them. The LED output port is mapped to an external interface, LEDs General Purpose [0:7], which connects to the LED hardware on the Zynq board.
2.1. Click Run This Task to run the Set Target Device and Synthesis Tool task.
2.2 In the Set Target > Set Target Interface task, choose AXI4-Lite for Blink_frequency, Blink_direction, and Read_back.
2.3 Choose LEDs General Purpose [0:7] for LED.
3. Generate the IP Core.
To generate the IP core, right-click the Generate RTL Code and IP Core task and select Run to Selected Task.
4. Generate and view the IP core report.
After you generate the custom IP core, the IP core files are in the ipcore folder within your project folder. An HTML custom IP core report is generated together with the custom IP core. The report describes the behavior and contents of the generated custom IP core.
In this part of the workflow, you insert your generated IP core into a embedded system reference design, generate an FPGA bitstream, and download the bitstream to the Zynq hardware.
The reference design is a predefined Xilinx EDK project. It contains all the elements the Xilinx software needs to deploy your design to the Zynq platform, except for the custom IP core and embedded software that you generate.
1. To integrate with the Xilinx EDK environment, select the Create Project task under Embedded System Integration, and click Run This Task. A Xilinx PlanAhead project with EDK embedded design is generated, and a link to the project is provided in the dialog window. You can optionally open up the project to take a look.
2. If you have an Embedded Coder license, you can generate a software interface model in the next task, Generate Software Interface Model. The details of the software interface model are explained in the next section of this example, "Generate a software interface model".
3. Build the FPGA bitstream in the Build FPGA Bitstream task. Make sure the Run build process externally option is checked, so the Xilinx synthesis tool will run in a separate process from MATLAB. Wait for the synthesis tool process to finish running in the external command window.
4. After the bitstream is generated, select the Program Target Device task and click Run This Task to program the Zynq hardware.
After you program the FPGA hardware, the LED starts blinking on your Zynq board. Next, you will generate C code to run on the ARM processor to control the LED blink frequency and direction.
In the HDL Workflow Advisor, after you generate the IP core and insert it into the EDK reference design, you can optionally generate a software interface model in the Embedded System Integration > Generate Software Interface Model task.
The software interface model contains the part of your design that runs in software. It includes all the blocks outside of the HDL subsystem, and replaces the HDL subsystem with AXI driver blocks. If you have an Embedded Coder license, you can automatically generate embedded code from the software interface model, build it, and run the executable on Linux on the ARM processor. The generated embedded software includes AXI driver code, generated from the AXI driver blocks, that controls the HDL IP core.
Run the Generate Software Interface Model task and see that a new model is generated. The task dialog shows a link to the model.
In the generated software interface model, the "led_counter" subsystem is replaced with the AXI driver blocks which generate the interface logic between the ARM processor and FPGA.
In this part of the workflow, you configure the generated software interface model, automatically generate embedded C code, and run your model on the ARM processor in the Zynq hardware in External mode.
When you are prototyping and developing an algorithm, it is useful to monitor and tune the algorithm while it runs on hardware. The External mode feature in Simulink enables this capability. In this mode, your algorithm is first deployed to the ARM processor in the Zynq hardware, and then automatically linked with the Simulink model on the host computer through Ethernet. The main role of the Simulink model is to tune and monitor the algorithm running on the hardware. Because the ARM processor is connected to the HDL IP core through AXI interface, you can use External mode to tune parameter and capture data from FPGA as well.
In the generated model, open the Configuration Parameters dialog box.
Select Solver and set "Stop Time" to "inf".
Under Code Generation > Interface, set "Interface" to "External mode". Set "Transport layer" to "tcpip". In "MEX-file arguments" enter the IP Address of your Zynq ZC702 hardware. For example, if IP Address of your Zynq ZC702 hardware is 192.168.1.10, enter '192.168.1.10'.
Click OK to save the settings and close dialog.
Click the Build button on the model toolstrip, or press Ctrl+B. After the build is done, a system command window will open that shows the messages coming from the model running on Zynq ZC702 hardware.
From the model menu, select Simulation > Mode > External. Next, select Simulation > Connect To Target. This will start the simulation and the scopes will plot data received from Zynq ZC702 hardware.
Double-click the Slider Gain block. Change the Slider Gain value and observe that the change in frequency of the LED array blinking on the ZC702 hardware. Doubleclick the Manual Switch block to switch direction of the blinking LEDs.
Doubleclick the scope connected to the Read_back output port and observe that the output data of the FPGA IP core is captured and sent back to Simulink scope.
When you are done changing model parameters, press the Stop button on the model. Observe that system command window opened in the previous step indicates that the model has been stopped. At this point, you may close the system command window.
This example shows how the hardware and software codesign workflow helps automate the deployment of your MATLAB and Simulink design to a Zynq-7000 All Programmable SoC. You can explore the best ways to partition and deploy your design by iterating through the workflow.
The following diagram shows the high-level picture of the workflow you went through in this example. To learn more about the hardware and software codesign workflow, please refer to the HDL Coder documentation: HDL Coder > HDL Coder Generation from Simulink > Deployment > Xilinx Zynq-7000 Platform > Concepts > Hardware and Software Codesign Workflow.