## Documentation |

This model shows how to use HDL Coder™ to check, generate, and verify HDL code for a fixed-point MIMO decoder model. Hardware implementation of a MIMO decoder is a demanding task because of the computational complexity of searching the closest points in an unstructured lattice in a multi-dimensional domain. The computational units are implemented using Simulink® blocks. The control unit is designed using MATLAB™ Function blocks.

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The decoding algorithm used in this example applies the Schnorr-Euchner method as the search strategy in the lattice decoder. For details on this algorithm, see the paper listed in the **Reference** section below.

The MIMO decoder implemented in this example models a 4 transmit and 4 receive wireless system with BPSK modulation. The channel matrix G, whose elements *Gij* represents the amplitude distortion from the *j*-th transmit antenna to the *i*-th receive antenna, are real zero mean Gaussian variables with variance 1 per dimension. The channel matrix used in the example is generated using the MATLAB® function *rng*() with a fixed seed, in this case 328800172, initialized in the InitFcn Model callback function of the Model Properties.

Changing the seed number will change the channel matrix. However, the requirements of the fixed-point data length in the MIMOdecoder module might be affected. Therefore a different bit error rate will be generated.

The model will not work correctly if the random number seed reset function is removed. The channel matrix is required to remain constant when the decoder is decoding a received vector (i.e. the *Decoder_Done* signal must be low).Extra logic is necessary to make the channel matrix time-varying.

**Performance Optimization Techniques**

This example also demonstrates design performance optimization techniques. Pipeline registers are added between Simulink blocks, for the purpose of driving synthesis tools to speed up the circuit frequency. The pipeline registers are implemented by the Integer Delay blocks after the Product blocks in the following module.

Because the lattice decoding algorithm implemented in this example is a various step searching algorithm, data control technique is applied to synchronize the search procedures. Each computing unit is controlled by an *Enable* signal generated from the embedded controller. A *Done* signal is returned to the controller when the computation with the unit is complete. The following picture shows the *Enable* and the *Done* signals.

Bit error rate calculated using the channel matrix used the example is plotted in the following figure.

E. Agrell, T. Eriksson, A. Vardy, and K. Zeger, "Closest point search in lattices," IEEE® Trans. Inf. Theory, vol. 48, no. 8, pp. 2201?2214, Aug. 2002.

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