HDL Coder

OFDM Receiver with 512-Point Streaming I/O FFT

This example shows how to use HDL Coder™ to check, generate, and verify HDL code for a 512-point HDL Optimized FFT block.

Introduction

This model implements a simple OFDM transmitter and receiver. The OFDM receiver part contains a 512-point Radix-2 DIT FFT to convert signal back to the frequency domain. There are two FFT implementations in this model:

  • The Simulink DSP FFT block is the FFT block in DSP System Toolbox™ library. It calculates a 512-point vector input each sample and works at a sample rate of 512.

  • The FFT HDL Optimized block is the FFT HDL Optimized block in DSP System Toolbox™ library. This implementation accepts both vector (NX1) or streaming complex input data and generates vector (NX1) or streaming complex results continuously after the initial pipelining latency. Vector mode is supported for simulation only. For HDL code generation the data must be streaming. To learn more about the HDL Optimized FFT block, please refer to the documentationdocumentation.

The results of the two FFT implementations are shown to be equal after matching the initial pipelining delay.

Additional Requirements:

  • Communications System Toolbox

  • DSP System Toolbox

% To open this example model, run the following command
open_system('hdlcoder_ofdm_fft');

sim('hdlcoder_ofdm_fft');

FFT Block Specification

  • Cooley-Tukey Radix-2 DIT FFT

  • Streaming I/O

  • 512 point

  • Data bitwidth: 12 bits

  • Complex fixed-point data type

  • Initial pipelining latency: 815 clock cycles

Check, Generate and Verify HDL

checkhdl( 'hdlcoder_ofdm_fft/HDL Optimized FFT');
makehdl(  'hdlcoder_ofdm_fft/HDL Optimized FFT');
makehdltb('hdlcoder_ofdm_fft/HDL Optimized FFT');

This concludes the OFDM Receiver with 512-Point Serial FFT example.