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Pipelined Configurable FIR

This example shows how to use HDL Coder™ to check, generate, and verify HDL for a pipelined configurable FIR filter using Simulink® and Stateflow®.

The CFIR system here is a configurable pipelined symmetric 32 tap FIR with the following characteristics:

     4 stage pipelined structure
     16 coefficient addressable registers
     4 adders/multipliers/accumulators in each stage of the filter

The finite state machine part of the system is modeled using a Stateflow chart and the datapath of the algorithm is implemented using generic Simulink blocks.

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