HDL Coder

Using IP Core Generation Workflow from Simulink: LED Blinking

This example shows how to use HDL Workflow Advisor to generate a custom HDL IP core which blinks LEDs on FPGA board. The generated IP core can be used on Xilinx® Zynq® platform, or on any Xilinx FPGA with MicroBlaze processor.

Introduction

Using the IP Core Generation workflow in the HDL Workflow Advisor enables you to automatically generate a sharable and reusable IP core module from a Simulink® model. The generated IP core is designed to be connected to an embedded processor on an FPGA device. HDL Coder™ generates HDL code from the Simulink® blocks, and also generates HDL code for the AXI interface logic connecting the IP core to the embedded processor. HDL Coder packages all the generated files into an IP core folder. You can then integrate the generated IP core with a larger FPGA embedded design in the Xilinx® EDK environment.

In this example, the DUT subsystem, led_counter, models a simple counter in order to blink the LEDs on an FPGA board. Two input ports, Blink_frequency and Blink_direction, are control ports which determine the LED blinking frequency and direction. You can use the Slider Gain or Manual Switch block to adjust the input values of these two ports. The embedded processor controls the generated IP core by writing to the generated AXI interface accessible registers. The output port, LED, is intended to connect to the actual LEDs. The output port, Read_Back, can be used to read data back to the processor.

open_system('hdlcoder_led_blinking');

Launch IP Core Generation Workflow

To launch the IP core generation workflow:

  1. Start the HDL Workflow Advisor from the hdlcoder_led_blinking/led_counter subsystem by right-clicking the led_counter subsystem, and choose HDL Code > HDL Workflow Advisor.

  2. In the Set Target > Set Target Device and Synthesis Tool task, for Target workflow, select IP Core Generation.

Configure Target Interface

Map each port in your DUT to one of the IP core target interfaces. In this example, input ports Blink_frequency and Blink_direction are mapped to the AXI4-Lite interface, so HDL Coder generates AXI interface accessible registers for them. The LED output port is mapped to an External Port, and can be connected to the actual LED device in the Xilinx EDK environment.

  1. Click Run This Task to run the Set Target Device and Synthesis Tool task.

  2. In the Set Target > Set Target Interface task, choose AXI4-Lite for Blink_frequency and Blink_direction.

  3. Choose External Port for LED.

Generate IP Core

To generate the IP core, right-click the Generate RTL Code and IP Core task and select Run to Selected Task.

IP Core Report

After you generate the custom IP core, the IP core files are in the ipcore folder within your project folder. An HTML custom IP core report is generated together with the custom IP core. The report describes the behavior and contents of the generated custom IP core.

Integrate with the Xilinx EDK environment

You can then integrate the generated IP core with a larger FPGA embedded design in the Xilinx EDK environment.

If you are targeting Xilinx Zynq® hardwares supported by HDL Coder Support Package for Xilinx Zynq-7000, you can select the board you are using in the Target platform option in the Set Target > Set Target Device and Synthesis Tool task. You can then use Embedded System Integration tasks in HDL Workflow Advisor to help you integrate the generated IP core into Xilinx EDK environment.

You can then observe the LED blinking on your FPGA board and use the embedded processor to control the blinking frequency and direction.