This example shows how to use the HDL Workflow Advisor to generate a custom HDL IP core which perform Sobel edge detection processing on streaming video.
Using the IP Core Generation workflow in the HDL Workflow Advisor enables you to automatically generate a sharable and reusable IP core module from a Simulink® model. The generated IP core is designed to be connected to an embedded processor on an FPGA device. HDL Coder™ generates HDL code from the Simulink blocks, and also generates HDL code for the AXI interface logic connecting the IP core to the embedded processor. HDL Coder packages all the generated files into an IP core folder. You can then integrate the generated IP core with a larger FPGA embedded design in the Xilinx® EDK environment.
In this example, the DUT subsystem, Sobel_HW, models a streaming Sobel edge detection algorithm. The input port Video_in and output port Video_out are data ports for video streams. Four input ports, Threshold, Sobel_Enable, Background_Color and Show_Gradient, are control ports to adjust the parameters the sobel edge detection algorithms. You can use the Slider Gain or Manual Switch block to adjust the input values of these ports. The embedded processor controls the generated IP core by writing to the generated AXI interface accessible registers.
modelname = 'hdlcoder_sobel_video'; open_system(modelname); sim(modelname);
To launch the IP core generation workflow:
Click the block Click to Use 1080p Source to change the video resolution parameter to 1920x1080, so you can generate an IP core to process 1080p video.
Start the HDL Workflow Advisor from the
hdlcoder_sobel_video/Sobel_HW subsystem by right-clicking the
Sobel_HW subsystem, and choose HDL Code > HDL Workflow Advisor.
In the Set Target > Set Target Device and Synthesis Tool task, for Target workflow, select IP Core Generation.
For Target platform, select Generic Xilinx Platform.
For Synthesis tool, select Xilinx ISE. If Xilinx ISE does not show up as a choice, use the hdlsetuptoolpath command to set up the Xilinx ISE synthesis tool path, and click the Refresh button.
Map each port in your DUT to one of the IP core target interfaces. In this example, the input port Video_in is mapped to AXI4-Stream Video In, and the output port Video_out is mapped to AXI4-Stream Video Out. Based on the mapping information, HDL Coder generates AXI4-Stream interface modules for these ports. The other control input ports are mapped to the AXI4-Lite interface, so HDL Coder generates AXI interface accessible registers for them.
Click Run This Task to run the Set Target Device and Synthesis Tool task.
In the Set Target > Set Target Interface task, choose AXI4-Stream Video In for Video_in.
Choose AXI4-Stream Video Out for Video_out.
Choose AXI4-Lite for Threshold, Sobel_Enable, Background_Color and Show_Gradient.
To generate the IP core, right-click the Generate RTL Code and IP Core task and select Run to Selected Task.
After you generate the custom IP core, the IP core files are in the ipcore folder within your project folder. An HTML custom IP core report is generated together with the custom IP core. The report describes the behavior and contents of the generated custom IP core.
You can then integrate the generated IP core with a larger FPGA embedded design in the Xilinx EDK environment.
If you are targeting Xilinx Zynq® ZC702 hardware, in the Set Target > Set Target Device and Synthesis Tool task, you can select Xilinx Zynq ZC702 evaluation kit for Target platform option. You can then use Embedded System Integration tasks in HDL Workflow Advisor to help you integrate the generated IP core into Xilinx Zynq Base Targeted Reference Design.