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Using Multiple Clocks in HDL Coder™

This example shows how to instantiate multiple top-level synchronous clock input ports in HDL Coder.

Overview of Clocking Modes

HDL Coder has two clocking modes: one that generates a single clock input to the Device Under Test (DUT), and one that will generate a synchronous primary clock input for each Simulink rate in the DUT. By default, HDL Coder creates an HDL design that uses a single clock port for the DUT. In single clock mode, if multiple rates exist in the Simulink model, a timing controller is created to control the clocking to the portions of the model that run at a slower rate. The timing controller generates a set of clock enables with the necessary rate and phase information to control the design. Each generated clock enable is an integer multiple slower than the primary clock rate. Each output signal rate is associated with a clock enable output signal that indicates the correct timing to sample the output data.

In synchronous multiple clock mode, the generated code has a set of clock ports as primary inputs to the DUT, each corresponding to a separate rate in the model. Transitions between rates often require clock enables at a given rate that are out of phase with that rate's clock. These out of phase signals are generated with a timing controller. A multiple clock model may require multiple timing controllers.

The first example uses a multirate CIC Interpolation filter in single clock mode. The filter's input is also presented as an output for this example to present a model with output signals running at different rates.

load_system('hdlcoder_clockdemo');
open_system('hdlcoder_clockdemo/DUT');
set_param('hdlcoder_clockdemo', 'SimulationCommand', 'update');

Single Clock Mode DUT Timing Interface

In single clock mode the HDL code for the DUT will have a set of three signals that do not appear in the Simulink diagram added to it. Collectively these are a clock bundle, containing signals for clock, master clock enable, and reset. These signals appear in the VHDL Entity declaration and are used throughout the generated code.

hdlset_param('hdlcoder_clockdemo', 'Traceability', 'on');
makehdl('hdlcoder_clockdemo/DUT');
### Generating HDL for 'hdlcoder_clockdemo/DUT'.
### Starting HDL check.
### Begin VHDL Code Generation for 'hdlcoder_clockdemo'.
### Working on DUT_tc as hdlsrc/hdlcoder_clockdemo/DUT_tc.vhd
### Working on hdlcoder_clockdemo/DUT as hdlsrc/hdlcoder_clockdemo/DUT.vhd
### Generating package file hdlsrc/hdlcoder_clockdemo/DUT_pkg.vhd
### Generating HTML files for code generation report in /tmp/R2014ad_522_6358/tpb3ec4d6b_c8a1_462f_9502_4285c23a508e/hdlsrc/hdlcoder_clockdemo/html/hdlcoder_clockdemo directory...
### Creating HDL Code Generation Check Report file:////tmp/R2014ad_522_6358/tpb3ec4d6b_c8a1_462f_9502_4285c23a508e/hdlsrc/hdlcoder_clockdemo/DUT_report.html
### HDL check for 'hdlcoder_clockdemo' complete with 0 errors, 0 warnings, and 1 message.
### HDL code generation complete.

Clock Summary Reporting in Single Clock Mode

The file comment block in the HDL DUT code contains Clock Summary information. In single clock mode as shown here, this report contains a table detailing the sample rates for each clock enable output signal. The report also contains a table listing each user output signal and its associated clock enable output signal. Any time a HTML report is generated, the Clock Summary Report is also generated.

Generating Synchronous Multiclock HDL Code

To generate multiple synchronous clocks for this design, the 'ClockInputs' parameter must be set to 'multiple'. This may be done on the makehdl command line or by changing the "Clock inputs" setting to "Multiple" on the HDL Configuration Parameters Global Settings tab.

makehdl('hdlcoder_clockdemo/DUT', 'ClockInputs', 'multiple');
### Generating HDL for 'hdlcoder_clockdemo/DUT'.
### Starting HDL check.
### Begin VHDL Code Generation for 'hdlcoder_clockdemo'.
### Working on DUT_tc_d1 as hdlsrc/hdlcoder_clockdemo/DUT_tc_d1.vhd
### Working on hdlcoder_clockdemo/DUT as hdlsrc/hdlcoder_clockdemo/DUT.vhd
### Generating package file hdlsrc/hdlcoder_clockdemo/DUT_pkg.vhd
### Generating HTML files for code generation report in /tmp/R2014ad_522_6358/tpb3ec4d6b_c8a1_462f_9502_4285c23a508e/hdlsrc/hdlcoder_clockdemo/html/hdlcoder_clockdemo directory...
### Creating HDL Code Generation Check Report file:////tmp/R2014ad_522_6358/tpb3ec4d6b_c8a1_462f_9502_4285c23a508e/hdlsrc/hdlcoder_clockdemo/DUT_report.html
### HDL check for 'hdlcoder_clockdemo' complete with 0 errors, 0 warnings, and 1 message.
### HDL code generation complete.

Clock Summary Information in Multiclock Mode

The contents of the Clock Summary are different in multiple clock mode. The report now contains a clock table. This table has one entry for each primary DUT clock. It describes the relative clock ratio between each clock and the fastest clock in the model. As with single clock mode, this information is presented both in the HDL DUT file comment block and the HTML report.

Multiclock Mode and HDL Coder Optimizations

Multiple synchronous clocks can be useful even for a design with only a single Simulink rate. Various optimizations can require clock rates faster than indicated in the original model. The following example demonstrates an audio filtering model that applies the same filter on the left and right channels. By default, HDL Coder would generate two filter modules in hardware. With this configuration, multiple clock mode still only generates one clock, just as single clock mode does.

bdclose hdlcoder_clockdemo;
load_system('hdlcoder_audiofiltering');
open_system('hdlcoder_audiofiltering/Audio filter');
hdlset_param('hdlcoder_audiofiltering', 'ClockInputs', 'Multiple');
hdlset_param('hdlcoder_audiofiltering/Audio filter', 'SharingFactor', 0);
makehdl('hdlcoder_audiofiltering/Audio filter', 'Traceability', 'on');
### Generating HDL for 'hdlcoder_audiofiltering/Audio filter'.
### Starting HDL check.
### Begin VHDL Code Generation for 'hdlcoder_audiofiltering'.
### Working on hdlcoder_audiofiltering/Audio filter/Filter_left as hdlsrc/hdlcoder_audiofiltering/Filter_left.vhd
### Working on hdlcoder_audiofiltering/Audio filter as hdlsrc/hdlcoder_audiofiltering/Audio_filter.vhd
### Generating HTML files for code generation report in /tmp/R2014ad_522_6358/tpb3ec4d6b_c8a1_462f_9502_4285c23a508e/hdlsrc/hdlcoder_audiofiltering/html/hdlcoder_audiofiltering directory...
### Creating HDL Code Generation Check Report file:////tmp/R2014ad_522_6358/tpb3ec4d6b_c8a1_462f_9502_4285c23a508e/hdlsrc/hdlcoder_audiofiltering/Audio_filter_report.html
### HDL check for 'hdlcoder_audiofiltering' complete with 0 errors, 0 warnings, and 0 messages.
### HDL code generation complete.

Using Multiple Clock Mode with Resource Sharing

With resource sharing applied to the identical left and right channel atomic subsystems, only one filter is generated. To meet the Simulink timing requirements, the single filter is run at twice the clock rate as the original Simulink model, as is shown below. Since the resource sharing optimization creates a second clock rate, the user can use synchronous multiple clock mode to provide external clocks for both rates. The Clock Summary Report shows the timing information for the two clocks.

bdclose gm_hdlcoder_audiofiltering;
hdlset_param('hdlcoder_audiofiltering/Audio filter', 'SharingFactor', 2);
makehdl('hdlcoder_audiofiltering/Audio filter', 'Traceability', 'on');
open_system('gm_hdlcoder_audiofiltering/Audio filter');
set_param('gm_hdlcoder_audiofiltering', 'SimulationCommand', 'update');
### Generating HDL for 'hdlcoder_audiofiltering/Audio filter'.
### Starting HDL check.
### The DUT requires an initial pipeline setup latency. Each output port experiences these additional delays.
### Output port 0: 1 cycles.
### Output port 1: 1 cycles.
### Begin VHDL Code Generation for 'hdlcoder_audiofiltering'.
### MESSAGE: The design requires 2 times faster clock with respect to the base rate = 0.00012207.
### Working on hdlcoder_audiofiltering/Audio filter/Filter_left as hdlsrc/hdlcoder_audiofiltering/Filter_left.vhd
### Working on mux1_serializer as hdlsrc/hdlcoder_audiofiltering/mux1_serializer.vhd
### Working on Filter_left0_deserializer as hdlsrc/hdlcoder_audiofiltering/Filter_left0_deserializer.vhd
### Working on Audio filter_tc_d1 as hdlsrc/hdlcoder_audiofiltering/Audio_filter_tc_d1.vhd
### Working on hdlcoder_audiofiltering/Audio filter as hdlsrc/hdlcoder_audiofiltering/Audio_filter.vhd
### Generating package file hdlsrc/hdlcoder_audiofiltering/Audio_filter_pkg.vhd
### Generating HTML files for code generation report in /tmp/R2014ad_522_6358/tpb3ec4d6b_c8a1_462f_9502_4285c23a508e/hdlsrc/hdlcoder_audiofiltering/html/hdlcoder_audiofiltering directory...
### Creating HDL Code Generation Check Report file:////tmp/R2014ad_522_6358/tpb3ec4d6b_c8a1_462f_9502_4285c23a508e/hdlsrc/hdlcoder_audiofiltering/Audio_filter_report.html
### HDL check for 'hdlcoder_audiofiltering' complete with 0 errors, 0 warnings, and 0 messages.
### HDL code generation complete.

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